AP105A272KQX2A datasheet, PDF - EEWORLD Datasheet

AP105A272KQX2A: DescriptionCeramic Capacitor, Multilayer, Ceramic, 50V, 10% +Tol, 10% -Tol, C0G, 30ppm/Cel TC, 0.0027uF, Surface Mount, 1210, CHIP; CategoryPassive components capacitor; File Size156KB，3 Pages; ManufacturerAVX

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AP105A272KQX2A Overview

Ceramic Capacitor, Multilayer, Ceramic, 50V, 10% +Tol, 10% -Tol, C0G, 30ppm/Cel TC, 0.0027uF, Surface Mount, 1210, CHIP

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	AVX
package instruction	, 1210
Reach Compliance Code	_compli
ECCN code	EAR99
capacitance	0.0027 µF
Capacitor type	CERAMIC CAPACITOR
dielectric materials	CERAMIC
high	0.94 mm
JESD-609 code	e0
length	3.2 mm
Manufacturer's serial number	APS
Installation features	SURFACE MOUNT
multi-layer	Yes
negative tolerance	10%
Number of terminals	2
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
Package shape	RECTANGULAR PACKAGE
Package form	SMT
method of packing	TR, PAPER, 7 INCH
positive tolerance	10%
Rated (DC) voltage (URdc)	50 V
series	AP10(3/5,NP0)
size code	1210
surface mount	YES
Temperature characteristic code	C0G
Temperature Coefficient	-/+30ppm/Cel ppm/°C
Terminal surface	Tin/Lead (Sn/Pb)
Terminal shape	WRAPAROUND
width	2.5 mm

Shortcut: L0 L1 L2 L3 L4 L5 L6 L7 L8 L9 LA LB LC LD LE LF LG LH LI LJ LK LL LM LN LO LP LQ LR LS LT LU LV LW LX LY LZ M0 M1 M2 M3 M4 M5 M6 M7 M8 M9 MA MB MC MD ME MF MG MH MI MJ MK ML MM MN MO MP MQ MR MS MT MU MV MW MX MY MZ N0 N1 N2 N3 N4 N5 N6 N7 N8 NA NB NC ND NE NF NG NH NI NJ NK NL NM NN NO NP NQ NR NS NT NU NV NX NZ O0 O1 O2 O3 OA OB OC OD OE OF OG OH OI OJ OK OL OM ON OP OQ OR OS OT OV OX OY OZ P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 PA PB PC PD PE PF PG PH PI PJ PK PL PM PN PO PP PQ PR PS PT PU PV PW PX PY PZ Q1 Q2 Q3 Q4 Q5 Q6 Q8 Q9 QA QB QC QE QF QG QH QK QL QM QP QR QS QT QV QW QX QY R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 RA RB RC RD RE RF RG RH RI RJ RK RL RM RN RO RP RQ RR RS RT RU RV RW RX RY RZ

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