EEWORLDEEWORLDEEWORLD

Part Number

Search
 PDF

ASM5P23S04AG-2-08-ST

Description
3.3V ‘SpreadTrak’ Zero Delay Buffer
Categorylogic    logic   
File Size422KB,15 Pages
ManufacturerPulseCore Semiconductor Corporation
Environmental Compliance
Download Datasheet Parametric View All

ASM5P23S04AG-2-08-ST Overview

3.3V ‘SpreadTrak’ Zero Delay Buffer

ASM5P23S04AG-2-08-ST Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
MakerPulseCore Semiconductor Corporation
package instruction0.150 INCH, GREEN, SOIC-8
Reach Compliance Codeunknow
series23S
Input adjustmentSTANDARD
JESD-30 codeR-PDSO-G8
JESD-609 codee3/e6
length4.9 mm
Logic integrated circuit typePLL BASED CLOCK DRIVER
Number of functions1
Number of inverted outputs
Number of terminals8
Actual output times4
Maximum operating temperature70 °C
Minimum operating temperature
Package body materialPLASTIC/EPOXY
encapsulated codeSOP
Package shapeRECTANGULAR
Package formSMALL OUTLINE
Peak Reflow Temperature (Celsius)260
Certification statusNot Qualified
Same Edge Skew-Max(tskwd)0.4 ns
Maximum seat height1.75 mm
Maximum supply voltage (Vsup)3.6 V
Minimum supply voltage (Vsup)3 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceMATTE TIN/TIN BISMUTH
Terminal formGULL WING
Terminal pitch1.27 mm
Terminal locationDUAL
Maximum time at peak reflow temperature40
width3.91 mm
minfmax133 MHz
[HC32F460 Development Board Review] 05. Recognition and processing of matrix buttons
The HC32F460 chip is equipped with a keyboard control module (KEYSCAN) that supports row and column scans of the matrix keyboard; the columns are driven by independent outputs KEYOUTm (m=0~7), while t...
xld0932 Domestic Chip Exchange
How to calculate the cost of surveillance installation and cleaning work
How to calculate the cost of surveillance installation and cleaning work...
qq102100 Security Electronics
100 Practical Tips for FPGA Design Experts
FPGA logic design has become a highly specialized hardware design field, which requires designers to master design tools, have a deep understanding of the internal structure of FPGAs, and flexibly use...
arui1999 Download Centre
Basic knowledge of third-order intermodulation
[size=4]Introduction to Passive Intermodulation[/size] [size=4] The problem of passive intermodulation interference has a long history in the communications industry and the RF connector industry. In ...
Aguilera RF/Wirelessly
MSP430 LaunchPad IO external interrupt
#includeint main( void ) { // Stop watchdog timer to prevent time out reset WDTCTL = WDTPW + WDTHOLD; P1DIR |= 0x01;//Set P1.0 port as output P1IE |= 0x08;//Enable P1.3 interrupt P1IES |= 0x08;//P1.3 ...
fish001 Microcontroller MCU
Is it true that the greater the memory depth of an oscilloscope, the better?
Is it true that the greater the memory depth of an oscilloscope, the better?...
牟允允 Integrated technical exchanges

Technical ResourceMore

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2024 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号