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X1M000341000811

Description
LVDS Output Clock Oscillator,
CategoryPassive components    oscillator   
File Size356KB,7 Pages
ManufacturerSeiko Epson Corporation
Download Datasheet Parametric View All

X1M000341000811 Overview

LVDS Output Clock Oscillator,

X1M000341000811 Parametric

Parameter NameAttribute value
MakerSeiko Epson Corporation
Reach Compliance Codeunknown
Other featuresENABLE/DISABLE FUNCTION; DIFFERENTIAL OUTPUT; TR, 7 INCH
maximum descent time0.0004 ns
Frequency Adjustment - MechanicalNO
frequency stability50%
Installation featuresSURFACE MOUNT
Nominal operating frequency133.33 MHz
Maximum operating temperature125 °C
Minimum operating temperature-55 °C
Oscillator typeLVDS
Output load100 OHM
physical size7.0mm x 5.0mm x 1.2mm
longest rise time0.0004 ns
Maximum supply voltage4 V
Minimum supply voltage-0.5 V
surface mountYES
maximum symmetry55/45 %
Clock OSC
XG-2102CA
XG-2102CA 133.330000MHz +/-50ppm LGRN
Product name
X1M0003410008xx
Product Number / Ordering code
Please refer to the 9.Packing information about xx (last 2 digits)
Output waveform
LVDS
Pb free / Complies with EU RoHS directive
Reference weight Typ. 133 mg
1.Absolute maximum ratings
Parameter
Symbol
Maximum supply voltage
Storage temperature
Input voltage
Min.
-0.5
-55
0
Typ.
-
-
-
Max.
4
125
0
Unit
V
ºC
V
Conditions / Remarks
-
Storage as single product
ST or OE Terminal
Vcc-GND
T_stg
Vin
2.Specifications(characteristics)
Parameter
Symbol
Output frequency
Supply voltage
Operating temperature
Frequency tolerance
Current consumption
Stand-by current
Disable current
Symmetry
Output voltage(LVDS)
Min.
-
-0.5
-55
-50
-
-
-
45
247
-
1.125
-
-
0.7Vcc
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-10
-
Typ.
133.3300
-
-
-
-
-
-
-
-
-
-
-
100
-
-
-
-
-
-
-
-
-
-
-
-
-45.1
-75.2
-106.5
-137.0
-149.4
-152.4
-
-
Max.
-
4
125
50
30
-
15.0
55
454
50
1.375
150
-
-
0.3Vcc
0.4
0.4
10
N/A
N/A
N/A
N/A
N/A
0.27
-
-
-
-
-
-
-
10
-
Unit
MHz
V
ºC
x10
-6
mA
mA
mA
%
mV
mV
V
mV
Conditions / Remarks
Clock OSC
-
Storage as single product
-
-
-
-
-
-
-
-
-
-
-
-
Output load condition(LVDS)
Input voltage
Rise time
Fall time
Start-up time
Jitter
Phase jitter
Phase noise
f0
Vcc
T_use
f_tol
Icc
I_std
I_dis
SYM
V
OD
dV
OD
Vos
dVos
L_LVDS
V
IH
V
IL
t
r
tf
t_str
t
DJ
T
RJ
t
RMS
t
p-p
t
acc
t
PJ
L(f)
ps
ps
ms
ps
ps
ps
ps
ps
ps
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
-
-
-
Deterministic Jitter
Random Jitter
δ(RMS of total distribution)
Peak to Peak
Accumulated Jitter(δ) n=2 to 50000 cycles
Off set Frequency: 12kHz to 20MHz
Off set 1Hz
Off set 10Hz
Off set 100Hz
Off set 1kHz
Off set 10kHz
Off set 100kHz
Off set 1MHz
Frequency aging
f_age
x10
-6
/Year
@+25ºC first year
-
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