SSP7200N
Elektronische Bauelemente
3 A, 200 V, R
DS(ON)
400 m
N-Channel Enhancement MOSFET
RoHS Compliant Product
A suffix of “-C” specifies halogen & lead-free
SOP-8PP
DESCRIPTION
These miniature surface mount MOSFETs utilize a high cell density trench process
to provide low R
DS(on)
and to ensure minimal power loss and heat dissipation.
Typical applications are DC-DC converters and power management in
portable and battery-powered products such as computers, printers,
PCMCIA cards, cellular and cordless telephones.
B
D
C
θ
e
E
FEATURES
Low R
DS(on)
provides higher efficiency and extends battery life.
Low thermal impedance copper leadframe SOP-8PP saves board
space.
Fast switching speed.
High performance trench technology.
d
A
b
g
F
G
Millimeter
Min.
Max.
1.00
1.10
5.70
5.80
0.20
0.30
3.61
3.98
5.40
6.10
0.08
0.20
3.60
3.99
Millimeter
Min.
Max.
0
°
12
°
0.33
0.51
1.27BSC
1.35
1.75
1.10
-
PRODUCT SUMMARY
PRODUCT SUMMARY
V
DS
(V)
200
R
DS
(on) (m
400@V
GS
= 10V
450@V
GS
= 4.5V
I
D
(A)
3.0
2.8
Gate
REF.
A
B
C
D
E
F
G
REF.
θ
b
d
e
g
Drain
Source
ABSOLUTE MAXIMUM RATINGS AND THERMAL DATA
(T
A
= 25°C unless otherwise specified)
PARAMETER
Drain-Source Voltage
Gate-Source Voltage
Continuous Drain Current
A
Pulsed Drain Current
B
Continuous Source Current (Diode Conduction)
A
Power Dissipation
A
T
A
=25°C
T
A
=70°C
SYMBOL
V
DS
V
GS
I
D
I
DM
I
S
RATING
200
20
3
2.4
50
2.3
5.0
3.2
-55 ~ 150
25
65
UNIT
V
V
A
A
A
W
°C
°C / W
T
A
=25°C
P
D
T
A
=70°C
Operating Junction and Storage Temperature Range
T
J
, T
STG
THERMAL RESISTANCE DATA
t≦10 sec
Maximum Junction to Ambient
A
R
θJA
Steady State
Notes
a.
b.
Surface Mounted on 1” x 1” FR4 Board.
Pulse width limited by maximum junction temperature.
http://www.SeCoSGmbH.com/
Any changes of specification will not be informed individually.
30-Jul-2010 Rev. A
Page 1 of 2
SSP7200N
Elektronische Bauelemente
3 A, 200 V, R
DS(ON)
400 m
N-Channel Enhancement MOSFET
ELECTRICAL CHARACTERISTICS
(T
A
=25°C unless otherwise specified)
PARAMETER
SYMBO MIN TYP MAX UNIT
Static
Gate-Threshold Voltage
Gate-Body Leakage
Zero Gate Voltage Drain Current
On-State Drain Current
A
Drain-Source On-Resistance
Forward Transconductance
A
Diode Forward Voltage
A
TEST CONDITIONS
V
GS(th)
I
GSS
I
DSS
I
D(ON)
R
DS(ON)
g
FS
V
SD
1
-
-
-
40
-
-
-
-
-
-
-
-
-
-
-
40
0.7
-
±
100
V
nA
μA
A
mΩ
S
V
V
DS
= V
GS
, I
D
= 250μA
V
DS
= 0V, V
GS
= 12V
V
DS
= 160V, V
GS
= 0V
V
DS
= 160V, V
GS
= 0V,T
J
=55
°C
V
DS
= 5V, V
GS
= 10V
V
GS
= 10V, I
D
= 3A
V
GS
= 4.5V, I
D
= 2.8A
V
DS
= 15V,
,
I
D
= 3A
I
S
= 2.3A, V
GS
= 0V
1
5
-
400
450
-
-
Dynamic
b
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Notes
a.
b.
Pulse test：PW
≦
300 us duty cycle
≦
2%.
Guaranteed by design, not subject to production testing.
Q
g
Q
gs
Q
gd
Td
(ON)
T
r
Td
(OFF)
T
f
-
-
-
-
-
-
-
15
3
5
15
10
54
26
-
-
-
-
-
-
-
nC
I
D
= 6A
V
DS
= 15V
V
GS
= 4.5V
I
D
= 1A, V
DD
= 15V
nS
V
GEN
= 10V
R
L
= 6Ω
http://www.SeCoSGmbH.com/
Any changes of specification will not be informed individually.
30-Jul-2010 Rev. A
Page 2 of 2
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