GS84118GB-100T datasheet, PDF - EEWORLD Datasheet

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GS84118GB-100T: DescriptionCache Tag SRAM, 256KX18, 12ns, CMOS, PBGA119, PLASTIC, BGA-119; Categorystorage storage; File Size719KB，30 Pages; ManufacturerGSI Technology; Websitehttp://www.gsitechnology.com/; Environmental Compliance

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GS84118GB-100T Overview

Cache Tag SRAM, 256KX18, 12ns, CMOS, PBGA119, PLASTIC, BGA-119

GS84118GB-100T Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	GSI Technology
Parts packaging code	BGA
package instruction	BGA,
Contacts	119
Reach Compliance Code	compliant
ECCN code	3A991.B.2.B
Maximum access time	12 ns
Other features	FLOW-THROUGH OR PIPELINED ARCHITECTURE
JESD-30 code	R-PBGA-B119
JESD-609 code	e1
length	22 mm
memory density	4718592 bit
Memory IC Type	CACHE TAG SRAM
memory width	18
Humidity sensitivity level	3
Number of functions	1
Number of terminals	119
word count	262144 words
character code	256000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	256KX18
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Package shape	RECTANGULAR
Package form	GRID ARRAY
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	260
Certification status	Not Qualified
Maximum seat height	2.4 mm
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	3.135 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	TIN SILVER COPPER
Terminal form	BALL
Terminal pitch	1.27 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED
width	14 mm

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GS84118T/B-166/150/133/100

TQFP, BGA

Commercial Temp

Industrial Temp

Features

• 3.3 V +10%/–5% core power supply, 2.5 V or 3.3 V I/O

supply

• Intergrated data comparator for Tag RAM application

• FT mode pin for flow through or pipeline operation

• LBO pin for Linear or Interleave (Pentium

and X86) Burst

mode

• Synchronous address, data I/O, and control inputs

• Synchronous Data Enable (DE)

• Asynchronous Output Enable (OE)

• Asynchronous Match Output Enable (MOE)

• Byte Write (BWE) and Global Write (GW) operation

• Three chip enable signals for easy depth expansion

• Internal self-timed write cycle

• JTAG Test mode conforms to IEEE standard 1149.1

• JEDEC-standard 100-lead TQFP package and 119-BGA:

T:TQFP or B: BGA

-166

Pipeline

3-1-1-1

Flow

Through

2-1-1-1

cycle

6.0 ns

3.5 ns

310 mA

8.5 ns

10 ns

190 mA

-150

6.6 ns

3.8 ns

275 mA

10 ns

190 mA

-133

7.5 ns

4.0 ns

250 mA

11 ns

15 ns

140 mA

-100

10 ns

4.5 ns

190 mA

12 ns

15 ns

140 mA

256K x 18 Sync

Cache Tag

166 MHz–100 MHz

8.5 ns–12 ns

3.3 V V

3.3 V and 2.5 V I/O

Output registers and the Match output register are provided and

controlled by the FT mode pin (Pin 14). Through use of the FT

mode pin, I/O registers can be programmed to perform pipeline

or flow through operation. Flow Through mode reduces

latency.

Byte write operation is performed by using Byte Write Enable

(BWE) input combined with two individual byte write signals

BW1-2. In addition, Global Write (GW) is available for

writing all bytes at one time.

Compare cycles begin as a read cycle with output disabled so

that compare data can be loaded into the data input register.

The comparator compares the read data with the registered

input data and a match signal is generated. The match output

can be either in Pipeline or Flow Through modes controlled by

the FT signal.

Low power (Standby mode) is attained through the assertion of

the ZZ signal, or by stopping the clock (CLK). Memory data is

retained during Standby mode.

JTAG boundary scan interface is provided using IEEE

standard 1149.1 protocol. Four pins—Test Data In (TDI), Test

Data Out (TDO), Test Clock (TCK) and Test Mode Select

(TMS)—are used to perform JTAG function.

The GS84118 operates on a 3.3 V power supply and all inputs/

outputs are 3.3 V- or 2.5 V-LVTTL-compatible. Separate

output (V

DDQ

) pins are used to allow both 3.3 V or 2.5 V IO

interface.

Functional Description

The GS84118 is a 256K x 18 high performance synchronous

SRAM with integrated Tag RAM comparator. A 2-bit burst

counter is included to provide burst interface with Pentium

and other high performance CPUs. It is designed to be used as

a Cache Tag SRAM, as well as data SRAM. Addresses, data

IOs, match output, chip enables (CE1, CE2, CE3), address

control inputs (ADSP, ADSC, ADV), and write control inputs

(BW1, BW2, BWE, GW, DE) are synchronous and are

controlled by a positive-edge-triggered clock (CLK).

Output Enable (OE), Match Output Enable, and power down

control (ZZ) are asynchronous. Burst can be initiated with

either ADSP or ADSC inputs. Subsequent burst addresses are

generated internally and are controlled by ADV. The burst

sequence is either interleave order (Pentium

or x86) or

linear order, and is controlled by LBO.

Rev: 1.05 7/2001

1/30

* Pentium is a trademark of Intel Corp.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Trademark Notice (if any) Trademark of Giga Semiconductor, Inc. (GSI Technology).

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