SY87724LE
3.3V AnyRate
®
MUX/DEMUX Up to 2.7GHz
General Description
The SY87724L is a complete serial data multiplexer and
demultiplexer, capable of operating at up to 2.7GHz. The
device provides for muxing and demuxing to 4, 5, 8, or 10
bit wide buses.
The SY87724L can accept a synchronous code group or
octet boundary input, and uses this input for parallel data
alignment.
The SY87724L is manufactured in Micrel’s high
performance ASSET2™ silicon bipolar process.
Micrel provides a complete protocol transparent solution
with the AnyRate
®
SY87721L CDR/CMU SY87729L, and
the SY87724L integrated MUX/DEMUX.
Datasheets and support documentation can be found on
Micrel’s web site at www.micrel.com.
Features
•
Protocol transparent MUX/DEMUX operation up to
2.7GHz
•
Programmable to 4, 5, 8, or 10 bit parallel interfaces
•
Differential clock and serial inputs/outputs
•
Easily controlled by framer logic
•
Synchronous frame boundary indication
•
HSPC (High Speed PECL-Compatible) inputs and
outputs
•
3.3V power supply
•
Available in 80-pin EPAD-TQFP
Applications
•
•
•
•
•
•
OC-3, OC-12, OC-48, ATM, InfiniBand
Gigabit Ethernet
Fibre Channel, 2X Fibre Channel
SMPTE-259 and 292
Proprietary optical transport
ITU G. 975 Solutions
___________________________________________________________________________________________________________
System Block Diagram
AnyRate and AnyClock are registered trademarks of Micrel, Inc.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (
408
) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
January 2008
M9999-012508-A
hbwhelp@micrel.com
or (408) 955-1690
Micrel, Inc.
SY87724LE
Pin Description
COMMON
LPBK – TTL Input
This pin defines whether a device exhibits local loopback
or not, as per the following table. Loopback internally
connects MUX serial out to demux serial in, thus the
user may expect MUX side parallel data to appear on
the demux parallel output pins.
LPBK
0
1
Functioning
Loopback
Normal
previously set boundary, the DPOUTCK± signal will
always occur later than would be expected. That is,
there will never be a short DPOUTCK± pulse.
DP0± through DP4± – Differential PECL Output
These signals may be used as either differential, or
single-ended. When converting to 4 or 5 bits, speed
issues may encourage the use of these signals
differentially. When converting to wider than 5 bits, these
signals are to be used single-ended. Please refer to the
applications section for further details.
DP5 through DP9 – PECL Output
These are the rest of the parallel output bits, to be used
when converting to wider than 5 bits. Which bits are valid
depends on the values of SIZ0, SIZ1, and SIZ2. Please
refer to the table in the applications section for further
details.
DPOUTCK± – Differential HSPC Output
This signal is used to strobe the DP0-9 data. It is used
differentially when converting to 4 or 5 bits, and is used
single-ended when converting to wider than 5 bits. The
clock rate of the line will be determined by the DCKIN
signal, and by the setting of the SIZ bits. This output
always provides valid differential logic levels.
MUX
MP0-9 – PECL Input
These bits accept data for muxing wider than 5 bits.
MPINCK+, used single-ended, determines when this
data may change. Please refer to the table in the
description for which pins represent what bits for various
widths.
MPF0–4± – Differential PECL Input
These signals are used when muxing 4 or 5 bits of
parallel data. MPINCK± determines when this data may
change. Please refer to the MUX table in the description
for which pins represent what bits for various widths.
MTXCLK± – Differential HSPC Input
This is the serial rate clock input to the MUX. It
determines the rate at which serial data will be shifted
out of the MUX.
MSOUT± – Differential PECL Output
This signal is the serialized data output.
Table 1. LPBK Input Pin Function
SIZ0, SIZ1, SIZ2 – TTL Input
These three signals determine the width of the parallel
output, as well as the width of parallel input. The
following table describes the parallel width options.
Width
4
5
8
10
Undefined
Note:
1. Pin 8 (SIZ2) should always be tied to a TTL logic level LOW.
SIZ0
0
1
0
1
X
SIZ1
0
0
1
1
X
SIZ2
0
0
0
0
1
(1)
Table 2. SIZ0, SIZ1, SIZ2 Input Truth Table
DEMUX
DSIN± – Differential HSPC Input
This is the serial input to the SY87724L demux. It
accepts the serial data and converts it to parallel data. It
is ignored during loopback.
DCKIN± – Differential HSPC Input
This is the bit rate clock that feeds serial data into the
demux shift register. This signal also feeds the demux
strobe generator and primary divider, except during
loopback.
DFMIN± – Differential HSPC Input
This is the frame alignment input signal. This signal
resets the primary divider, as well as the strobe
generator. This effectively sets the alignment for the
parallel data being demuxed. Usually, DFMIN± asserts
one DCKIN± before a parallel word boundary, and
continues to assert one clock before every boundary.
However, DFMIN± need only occur once for proper
operation. Should DFMIN± assert at other than a
January 2008
5
M9999-012508-A
hbwhelp@micrel.com
or (408) 955-1690
Altera SoC
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