K6T1008V2C, K6T1008U2C Family
Document Title
128K x8 bit Low Power and Low Voltage CMOS Static RAM
CMOS SRAM
Revision History
Revision No. History
0.0
1.0
Initial draft
Finalize
- Increased I
SB
, I
DR
Commercial part = 10µA
Industrial part = 20µ
A
Revise
- Change speed bin
KM68V1000C Family: 70/85ns
→
70/100ns
KM68U1000C Family: 70/100ns
→
85/100ns
- Improved operating current: 40mA
→
35mA
- Improved power dissipation
P
D
: 0.7W
→
1.0W
- Improved standby current
Extended/Industrial: 20
→
10µ
A
- VIL: 0.4V
→
0.6V
Draft Data
July 3, 1996
December 16, 1996
Remark
Preliminary
Final
2.0
November 25, 1997
Final
The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserves the right to change the specifications and
products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices.
1
Revision 2.0
November 1997
K6T1008V2C, K6T1008U2C Family
128K x8 bit Low Power and Low Voltage CMOS Static RAM
FEATURES
•
Process Technology: 0.4µm CMOS
•
Organization: 128K x8
•
Power Supply Voltage:
K6T1008V2C family: 3.0~3.6V
K6T1008U2C family: 2.7~3.3V
•
Low Data Retention Voltage: 2V(Min)
•
Three state output and TTL Compatible
•
Package Type: 32-SOP-525, 32-TSOP1-0820F/R,
32-TSOP1-0813.4F/R
CMOS SRAM
GENERAL DESCRIPTION
The K6T1008V2C and K6T1008U2C families are fabricated by
SAMSUNG′s advanced CMOS process technology. The fami-
lies support various operating temperature ranges and have
various package types for user flexibility of system design. The
families also supports low data retention voltage for battery
back-up operation with low data retention current.
PRODUCT FAMILY
Power Dissipation
Product Family
K6T1008V2C-B
K6T1008U2C-B
K6T1008V2C-D
K6T1008U2C-D
K6T1008V2C-F
K6T1008U2C-F
Industrial(-40~85°C)
Extended(-25~85°C)
Operating Temperature
Vcc Range
3.0~3.6V
2.7~3.3V
3.0~3.6V
2.7~3.3V
3.0~3.6V
2.7~3.3V
Speed
70/100ns
85/100ns
70/100ns
85/100ns
70/100ns
85/100ns
10µA
35mA
32-SOP
32-TSOP1-F/R
32-sTSOP1-F/R
Standby
(I
SB1
, Max)
Operating
(I
CC2
, Max)
PKG Type
Commercial(0~70°C)
PIN DESCRIPTION
A11
A9
A8
A13
WE
VCC CS2
A15
A15 VCC
CS2 NC
A16
WE A14
A12
A13 A7
A6
A8
A5
A9
A4
A11
OE
A4
A10 A5
A6
CS1 A7
I/O8 A12
A14
I/O7 A16
NC
I/O6
VCC
I/O5 A15
CS2
I/O4 WE
A13
A8
A9
A11
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
A3
A2
A1
A0
I/O1
I/O2
I/O3
VSS
I/O4
I/O5
I/O6
I/O7
I/O8
CS1
A10
OE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
A10
CS1
I/O8
I/O7
I/O6
I/O5
I/O4
VSS
I/O3
I/O2
I/O1
A0
A1
A2
A3
FUNCTIONAL BLOCK DIAGRAM
Clk gen.
Precharge circuit.
N.C
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O1
I/O2
I/O3
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
A4
A5
A6
A7
A8
A12
A13
A14
A15
A16
32-TSOP
32-
S
TSOP
Type1-Forward
V
CC
V
SS
Memory array
1024 rows
128×8 columns
Row
select
32-SOP
25
24
23
22
21
20
19
18
17
I/O
1
I/O
8
32-TSOP
32-
S
TSOP
Type1-Reverse
Data
cont
I/O Circuit
Column select
A10 A0
A1
A2 A3 A9
A11
Name
CS
1
, CS
2
OE
WE
A
0
~A
16
I/O
1
~I/O
8
Vcc
Vss
N.C
Function
Chip Select Inputs
Output Enable Input
Write Enable Input
Address Inputs
Data Inputs/Outputs
Power
Ground
No Connection
CS1
CS2
WE
OE
Control
logic
SAMSUNG ELECTRONICS CO., LTD.
reserves the right to change products and specifications without notice.
Revision 2.0
November 1997
2
K6T1008V2C, K6T1008U2C Family
PRODUCT LIST
Commercial Temperature Products
(0~70°C)
Part Name
K6T1008V2C-GB70
K6T1008V2C-GB10
K6T1008V2C-TB70
K6T1008V2C-TB10
K6T1008V2C-RB70
K6T1008V2C-RB10
K6T1008U2C-GB85
K6T1008U2C-GB10
K6T1008U2C-TB85
K6T1008U2C-TB10
K6T1008U2C-RB85
K6T1008U2C-RB10
K6T1008V2C-YB70
K6T1008V2C-YB10
K6T1008V2C-NB70
K6T1008V2C-NB10
K6T1008U2C-YB85
K6T1008U2C-YB10
K6T1008U2C-NB85
K6T1008U2C-NB10
CMOS SRAM
Industrial Temperature Products
(-40~85°C)
Part Name
K6T1008V2C-GF70
K6T1008V2C-GF10
K6T1008V2C-TF70
K6T1008V2C-TF10
K6T1008V2C-RF70
K6T1008V2C-RF10
K6T1008U2C-GF85
K6T1008U2C-GF10
K6T1008U2C-TF85
K6T1008U2C-TF10
K6T1008U2C-RF85
K6T1008U2C-RF10
K6T1008V2C-YF70
K6T1008V2C-YF10
K6T1008V2C-NF70
K6T1008V2C-NF10
K6T1008U2C-YF85
K6T1008U2C-YF10
K6T1008U2C-NF85
K6T1008U2C-NF10
Extended Temperature Products
(-25~85°C)
Part Name
K6T1008V2C-GD70
K6T1008V2C-GD10
K6T1008V2C-TD70
K6T1008V2C-TD10
K6T1008V2C-RD70
K6T1008V2C-RD10
K6T1008U2C-GD85
K6T1008U2C-GD10
K6T1008U2C-TD85
K6T1008U2C-TD10
K6T1008U2C-RD85
K6T1008U2C-RD10
K6T1008V2C-YD70
K6T1008V2C-YD10
K6T1008V2C-ND70
K6T1008V2C-ND10
K6T1008U2C-YD85
K6T1008U2C-YD10
K6T1008U2C-ND85
K6T1008U2C-ND10
Function
32-SOP, 70ns, 3.3V
32-SOP, 100ns, 3.3V
32-TSOP F, 70ns, 3.3V
32-TSOP F, 100ns, 3.3V
32-TSOP R, 70ns, 3.3V
32-TSOP R, 100ns, 3.3V
32-SOP, 85ns, 3.0V
32-SOP, 100ns, 3.0V
32-TSOP F, 85ns, 3.0V
32-TSOP F, 100ns, 3.0V
32-TSOP R, 85ns, 3.0V
32-TSOP R, 100ns, 3.0V
32-sTSOP F, 70ns, 3.3V
32-sTSOP F, 100ns, 3.3V
32-sTSOP R, 70ns, 3.3V
32-sTSOP R, 100ns, 3.3V
32-sTSOP F, 85ns, 3.0V
32-sTSOP F, 100ns, 3.0V
32-sTSOP R, 85ns, 3.0V
32-sTSOP R, 100ns, 3.0V
Function
32-SOP, 70ns, 3.3V
32-SOP, 100ns, 3.3V
32-TSOP F, 70ns, 3.3V
32-TSOP F, 100ns, 3.3V
32-TSOP R, 70ns, 3.3V
32-TSOP R, 100ns, 3.3V
32-SOP, 85ns, 3.0V
32-SOP, 100ns, 3.0V
32-TSOP F, 85ns, 3.0V
32-TSOP F, 100ns, 3.0V
32-TSOP R, 85ns, 3.0V
32-TSOP R, 100ns, 3.0V
32-sTSOP F, 70ns, 3.3V
32-sTSOP F, 100ns, 3.3V
32-sTSOP R, 70ns, 3.3V
32-sTSOP R, 100ns, 3.3V
32-sTSOP F, 85ns, 3.0V
32-sTSOP F, 100ns, 3.0V
32-sTSOP R, 85ns, 3.0V
32-sTSOP R, 100ns, 3.0V
Function
32-SOP, 70ns, 3.3V
32-SOP, 100ns, 3.3V
32-TSOP F, 70ns, 3.3V
32-TSOP F, 100ns, 3.3V
32-TSOP R, 70ns, 3.3V
32-TSOP R, 100ns, 3.3V
32-SOP, 85ns, 3.0V
32-SOP, 100ns, 3.0V
32-TSOP F, 85ns, 3.0V
32-TSOP F, 100ns, 3.0V
32-TSOP R, 85ns, 3.0V
32-TSOP R, 100ns, 3.0V
32-sTSOP F, 70ns, 3.3V
32-sTSOP F, 100ns, 3.3V
32-sTSOP R, 70ns, 3.3V
32-sTSOP R, 100ns, 3.3V
32-sTSOP F, 85ns, 3.0V
32-sTSOP F, 100ns, 3.0V
32-sTSOP R, 85ns, 3.0V
32-sTSOP R, 100ns, 3.0V
FUNCTIONAL DESCRIPTION
CS
1
H
X
1)
L
L
L
CS
2
X
1)
L
H
H
H
OE
X
1)
X
1)
H
L
X
1)
WE
X
1)
X
1)
H
H
L
I/O Pin
High-Z
High-Z
High-Z
Dout
Din
Mode
Deselected
Deselected
Output Disabled
Read
Write
Power
Standby
Standby
Active
Active
Active
1. X means don′t care(Must be in high or low status.)
ABSOLUTE MAXIMUM RATINGS
1)
Item
Voltage on any pin relative to Vss
Voltage on Vcc supply relative to
Power Dissipation
Storage temperature
Operating Temperature
Symbol
V
IN
,V
OUT
V
CC
P
D
T
STG
T
A
Ratings
-0.5 to V
CC
+0.5
-0.3 to 4.6
1.0
-65 to 150
0 to 70
-25 to 85
-40 to 85
Soldering temperature and time
T
SOLDER
260°C, 10sec (Lead Only)
Unit
V
V
W
°C
°C
°C
°C
-
Remark
-
-
-
-
K6T1008V2C-B/K6T1008U2C-B
K6T1008V2C-D/K6T1008U2C-D
K6T1008V2C-F/K6T1008U2C-F
-
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be
restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
3
Revision 2.0
November 1997
K6T1008V2C, K6T1008U2C Family
RECOMMENDED DC OPERATING CONDITIONS
1)
Item
Supply voltage
Ground
Input high voltage
Input low voltage
Symbol
Vcc
Vss
V
IH
V
IL
Product
K6T1008V2C Family
K6T1008U2C Family
All Family
K6T1008V2C, K6T1008U2C Family
K6T1008V2C, K6T1008U2C Family
Min
3.0
2.7
0
2.2
-0.3
3)
CMOS SRAM
Typ
3.3
3.0
0
-
-
Max
3.6
3.3
0
Vcc+0.3
2)
0.6
Unit
V
V
V
V
1. Commercial Product: T
A
=0 to 70°C, unless otherwise specified
Extended Product: T
A
=-25 to 85°C, unless otherwise specified
Industrial Product: T
A
=-40 to 85°C, unless otherwise specified
2. Overshoot: V
CC
+3.0V in case of pulse width
≤30ns
3. Undershoot: -3.0V in case of pulse width
≤30ns
4. Overshoot and undershoot is sampled, not 100% tested.
CAPACITANCE
1)
(f=1MHz, TA=25°C)
Item
Input capacitance
Input/Output capacitance
1
. Capacitance is sampled, not 100% tested
Symbol
C
IN
C
IO
Test Condition
V
IN
=0V
V
IO
=0V
Min
-
-
Max
6
8
Unit
pF
pF
DC AND OPERATING CHARACTERISTICS
Item
Input leakage current
Output leakage current
Operating power supply
Average operating current
Symbol
I
LI
I
LO
I
CC
I
CC1
I
CC2
Output low voltage
Output high voltage
Standby Current(TTL)
Standby Current(CMOS)
V
OL
V
OH
I
SB
I
SB1
V
IN
=Vss to Vcc
CS
1
=V
IH
or CS
2
=V
IL
or OE=V
IH
or WE=V
IL,
V
IO
=Vss to Vcc
I
IO
=0mA, CS
1
=V
IL
, CS
2
=V
IH
, V
IN
=V
IL
or V
IH
, Read
Cycle time=1µs, 100% duty, I
IO
=0mA,
CS
1
≤0.2V,
CS
2
≥V
CC
-0.2V, V
IN
≤0.2V
or V
IN
≥V
CC
-0.2V
Read
Write
-
-
2.2
-
-
Test Conditions
Min
-1
-1
-
-
Typ
-
-
2
1.5
10
25
-
-
-
0.3
Max
1
1
5
5
15
35
0.4
-
0.3
10
mA
V
V
mA
µA
Unit
µA
µA
mA
mA
Cycle time=Min, 100% duty, I
IO
=0mA, CS
1
=V
IL
, CS
2
=V
IH
, V
IN
=V
IL
or V
IH
I
OL
=2.1mA
I
OH
=-1.0mA
CS
1
=V
IH,
CS
2
=V
IL
,
Other inputs=V
IL
or V
IH
CS
1
≥Vcc-0.2V,
CS
2
≥Vcc-0.2V
or CS
2
≤0.2V,
Other inputs=0~Vcc
4
Revision 2.0
November 1997
K6T1008V2C, K6T1008U2C Family
AC OPERATING CONDITIONS
TEST CONDITIONS
(Test Load and Input/Output Reference)
Input pulse level: 0.4 to 2.2V
Input rising and falling time: 5ns
Input and output reference voltage:1.5V
Output load(see right): C
L
=100pF+1TTL
C
L
1)
CMOS SRAM
1. Including scope and jig capacitance
AC CHARACTERISTICS
(Commercial product:T
A
=0 to 70°C, Extended product:T
A
=-25 to 85°C, Industrial product: T
A
=-40 to 85°C
K6T1008V2C Family: Vcc=3.0~3.6V, K6T1008U2C Family: Vcc=2.7~3.3V)
Speed Bins
Parameter List
Symbol
70ns
Min
Read cycle time
Address access time
Chip select to output
Output enable to valid output
Read
Chip select to low-Z output
Output enable to low-Z output
Chip disable to high-Z output
Output disable to high-Z output
Output hold from address change
Write cycle time
Chip select to end of write
Address set-up time
Address valid to end of write
Write
Write pulse width
Write recovery time
Write to output high-Z
Data to write time overlap
Data hold from write time
End write to output low-Z
t
RC
t
AA
t
CO1
, t
CO2
t
OE
t
LZ
t
OLZ
t
HZ
t
OHZ
t
OH
t
WC
t
CW
t
AS
t
AW
t
WP
t
WR
t
WHZ
t
DW
t
DH
t
OW
70
-
-
-
10
5
0
0
10
70
60
0
60
55
0
0
30
0
5
Max
-
70
70
35
-
-
25
25
-
-
-
-
-
-
-
25
-
-
-
Min
85
-
-
-
10
5
0
0
15
85
70
0
70
60
0
0
35
0
5
85ns
Max
-
85
85
40
-
-
25
25
-
-
-
-
-
-
-
30
-
-
-
100ns
Min
100
-
-
-
10
5
0
0
15
100
80
0
80
70
0
0
40
0
5
Max
-
100
100
50
-
-
30
30
-
-
-
-
-
-
-
30
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Units
DATA RETENTION CHARACTERISTICS
Item
Vcc for data retention
Data retention current
Data retention set-up time
Recovery time
Symbol
V
DR
I
DR
t
SDR
t
RDR
CS
1
1)
≥Vcc-0.2V
Vcc=3.0V, CS
1
≥Vcc-0.2V
,
CS
2
≥V
CC
-0.2V, or CS
2
≤0.2V
See data retention waveform
Test Condition
1)
Min
2.0
-
0
5
Typ
-
0.3
-
-
Max
3.6
5
-
-
Unit
V
µA
ms
1. CS
1
≥Vcc-0.2V
,
CS
2
≥V
CC
-0.2V, or CS
2
≤0.2V
5
Revision 2.0
November 1997
Download Centre
京公网安备 11010802033920号
EEWORLD
