W24L11
128K
×
8 CMOS STATIC RAM
GENERAL DESCRIPTION
The W24L11 is a normal-speed, very low-power CMOS static RAM organized as 131072
×
8 bits that
operates on a wide voltage range from 3.3V to 5V power supply. This device is manufactured using
Winbond's high performance CMOS technology.
FEATURES
•
•
•
•
•
•
Low power consumption
Access time: 55/70 nS
3.3V/5V power supply
Fully static operation
All inputs and outputs directly TTL compatible
Three-state outputs
•
Battery back-up operation capability
•
Data retention voltage: 2V (min.)
•
Packaged 450 mil SOP, standard type one,
TSOP (8 mm
×
20 mm), small type one and
TSOP (8 mm
×
13.4 mm)
PIN CONFIGURATIONS
BLOCK DIAGRAM
CLK GEN.
A16
A14
PRECHARGE CKT.
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O1
I/O2
I/O3
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
V
DD
A15
CS2
A12
A4
A3
A2
R
O
W
D
E
C
O
D
E
R
CORE CELL ARRAY
1024 ROWS
128 X 8 COLUMNS
#WE
A13
A8
A9
A11
#OE
A10
A7
A6
A5
A9
32-pin
SOP
25
24
23
22
21
20
19
18
17
I/O1
:
I/O8
DATA
CNTRL.
CLK
GEN.
I/O CKT.
COLUMN DECODER
#WE
#CS1
I/O8
A15 A13 A8 A1 A0 A11A10
#CS1
CS2
#OE
I/O7
I/O6
I/O5
I/O4
PIN DESCRIPTION
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
#OE
A10
#CS1
I/O8
I/O7
I/O6
I/O5
I/O4
V
SS
I/O3
I/O2
I/O1
A0
A1
A2
A3
A11
A9
A8
A13
#WE
CS2
A15
V
DD
NC
A16
A14
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32-pin
TSOP
SYMBOL
A0−A16
I/O1−I/O8
#CS1, CS2
#WE
#OE
V
DD
V
SS
NC
DESCRIPTION
Address Inputs
Data Inputs/Outputs
Chip Select Input
Write Enable Input
Output Enable Input
Power Supply
Ground
No Connection
-1-
Publication Release Date: August 7, 2001
Revision A4
W24L11
TRUTH TABLE
#CS1
H
X
L
L
L
CS2
X
L
H
H
H
#OE
X
X
H
L
X
#WE
X
X
H
H
L
MODE
Not Selected
Not Selected
Output Disable
Read
Write
I/O1−I/O8
High Z
High Z
High Z
Data Out
Data In
V
DD
CURRENT
I
SB
, I
SB1
I
SB
, I
SB1
I
DD
I
DD
I
DD
DC CHARACTERISTICS
Absolute Maximum Ratings
PARAMETER
3.3V
Supply Voltage to V
SS
Potential
Input/Output to V
SS
Potential
Allowable Power Dissipation
Storage Temperature
Operating Temperature
L/LL
LE
-0.5 to +4.6
1.0
-65 to +150
0 to 70
-20 to 85
RATING
5V
-0.5 to +7.0
V
V
W
°C
°C
UNIT
-0.5 to V
DD
+0.5
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability
of the device.
Operating Characteristics
(V
DD
= 5V
±10%;
V
DD
= 3.3V
±5%;
V
SS
= 0V; T
A
(°C) = 0 to 70 for LL, -20 to 85 for LE)
PARAMETER
Input Low Voltage
SYM.
V
IL
TEST CONDITIONS
-
3.3V
5V
MIN.
-0.5
-0.5
+2.0
-1
-1
MAX.
+0.6
+0.8
V
DD
+0.5
+1
+1
UNIT
V
Input High Voltage
Input Leakage Current
Output Leakage Current
V
IH
I
LI
I
LO
-
V
IN
= V
SS
to V
DD
VI/O = V
SS
to V
DD
,
#CS1 = V
IH
(min.) or
CS2 = V
IL
(max.) or
#OE = V
IH
(min.) or
#WE = V
IL
(max.)
I
OL
= +2.1 mA
V
µ
A
µ
A
Output Low Voltage
V
OL
-
0.4
V
-2-
W24L11
Operating Characteristics, continued
PARAMETER
Output High Voltage
Operating Power
Supply Current
SYM.
V
OH
I
DD
TEST CONDITIONS
I
OH
= -1.0 mA
55
#CS1= VIL (max.) and
CS2 = VIH (min.),
I/O = 0 mA,
70
Cycle = min. Duty =100%
2.2
-
-
-
3.3V
MIN.
MAX.
MIN.
5V
MAX.
UNIT
-
80
70
3
mA
V
mA
-
50
40
1
2.4
-
-
-
Standby Power
Supply Current
I
SB
I
SB1
#CS1=
V
IH
(min.) or
CS2 = V
IL
(max.)
Cycle = min. Duty = 100%
LL/LE
#CS1≥ VDD -0.2V
or CS2
≤
0.2V
L
-
-
50
100
-
-
50/70
100
µ
A
Note: Typical parameter is measured under ambient temperature T
A
= 25° C and V
DD
= 3.3V/5V
CAPACITANCE
(V
DD
= 5V
±10%;
V
DD
= 3.3V
±5%,
T
A
= 25° C, f = 1 MHz)
PARAMETER
Input Capacitance
Input/Output Capacitance
SYM.
C
IN
C
I/O
CONDITIONS
V
IN
= 0V
V
OUT
= 0V
MAX.
6
8
UNIT
pF
pF
Note: These parameters are sampled but not 100% tested.
AC Characteristics
AC Test Conditions
PARAMETER
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing Reference Level
Output Load
CONDITIONS
0V to 3.0V
5 nS
1.5V
See the drawing below
AC Test Loads and Waveform
1 TTL
OUTPUT
100 pF
Including
Jig and
Scope
OUTPUT
5 pF
Including
Jig and
Scope
(For T
CLZ,
T
OLZ,
T
CHZ,
T
OHZ,
T
WHZ,
T
OW
)
3.0 V
0V
5 nS
90%
10%
90%
10%
1 TTL
5 nS
-3-
Publication Release Date: August 7, 2001
Revision A4
W24L11
AC Characteristics, continued
(V
DD
= 5V
±10%;
V
DD
= 3.3V
±5%;
V
SS
= 0V; T
A
(°C) = 0 to 70 for LL, -20 to 85 for LE)
Read Cycle
PARAMETER
SYM.
55
MIN.
Read Cycle Time
Address Access Time
Chip Select Access Time
Output Enable to Output Valid
Chip Selection to Output in Low Z
Output Enable to Output in Low Z
Chip Deselection to Output in High Z
Output Disable to Output in High Z
Output Hold from Address Change
∗
These parameters are sampled but not 100% tested
3.3V/5V
70
MAX.
-
55
55
30
-
-
25
25
-
MIN.
70
-
-
-
10
5
-
-
10
MAX.
-
70
70
35
-
-
30
30
-
UNIT
T
RC
T
AA
T
ACS
T
AOE
T
CLZ
*
T
OLZ
*
T
CHZ
*
T
OHZ
*
T
OH
55
-
-
-
10
5
-
-
10
nS
nS
nS
nS
nS
nS
nS
nS
nS
Write Cycle
PARAMETER
SYM.
55
MIN.
Write Cycle Time
Chip Selection to End of Write
Address Valid to End of Write
Address Setup Time
Write Pulse Width
Write Recovery Time
#CS1, CS2
, #WE
3.3/5V
70
MAX.
-
-
-
-
-
0
-
-
25
25
-
MIN.
70
50
50
0
50
-
45/30
0
-
-
5
-
-
25
25
-
MAX.
-
-
-
-
-
UNIT
T
WC
T
CW
T
AW
T
AS
T
WP
T
WR
T
DW
T
DH
T
WHZ
*
T
OHZ
*
T
OW
55
40
40
0
45
0
40/25
0
-
-
5
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
Data Valid to End of Write
Data Hold from End of Write
Write to Output in High Z
Output Disable to Output in High Z
Output Active from End of Write
∗
These parameters are sampled but not 100% tested
-4-
W24L11
TIMING WAVEFORMS
Read Cycle 1
(Address Controlled)
T
RC
Address
T
OH
D
OUT
TAA
T
OH
Read Cycle 2
(Chip Select Controlled)
#CS1
CS2
T
ACS
TCLZ
T
CHZ
D
OUT
Read Cycle 3
(Output Enable Controlled)
T
RC
Address
T
AA
#OE
T
AOE
T
OLZ
#CS1
CS2
T
OH
T
ACS
D
OUT
T
CLZ
T
CHZ
T
OHZ
-5-
Publication Release Date: August 7, 2001
Revision A4
PCB Design
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