Product Specification
PE42540
Product Description
The PE42540 is a HaRP™ technology-enhanced
absorptive SP4T RF switch developed on UltraCMOS
®
process technology. This switch is designed specifically
to support the requirements of the test equipment and
ATE market. It is comprised of four symmetric RF ports
and has very high isolation. An on-chip CMOS decode
logic facilitates a two-pin low voltage CMOS control
interface and an optional external Vss feature. High
ESD tolerance and no blocking capacitor requirements
make this the ultimate in integration and ruggedness.
The PE42540 is manufactured on Peregrine’s
UltraCMOS
®
process, a patented variation of silicon-on-
insulator (SOI) technology on a sapphire substrate,
offering the performance of GaAs with the economy
and integration of conventional CMOS.
UltraCMOS
®
SP4T RF Switch
10 Hz - 8 GHz
Features
HaRP™ technology enhanced
Fast settling time
Eliminates gate and phase lag
No drift in insertion loss and phase
High linearity: 58 dBm IIP3
Low insertion loss: 0.8 dB @ 3 GHz,
1.0 dB @ 6 GHz and 1.2 dB @ 8 GHz
High isolation: 45 dB @ 3 GHz,
39 dB @ 6 GHz and 31 dB @ 8 GHz
Maximum power handling: 30 dBm @
8 GHz
High ESD tolerance of 2kV HBM on RFC
and 1kV HBM on all other pins
Figure 1. Functional Diagram
RFC
Figure 2. Package Type
32-lead 5x5 mm LGA
RF1
ESD
ESD
RF2
50
50
RF3
ESD
ESD
RF4
50
CMOS Control/
Driver and ESD
50
71-0067
V
DD
V1
V2
Vss
EXT
Document No. 70-0299-09
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©2010-2012 Peregrine Semiconductor Corp. All rights reserved.
Page 1 of 12
Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com
PE42540
Product Specification
Table 1. Electrical Specifications @ 25°C, V
DD
= 3.3V, Vss
EXT
= 0V (Z
S
= Z
L
= 50Ω)
Parameter
Operating Frequency
10 Hz-9 kHz
3000 MHz
6000 MHz
7500 MHz
8000 MHz
10 Hz-9 kHz
3000 MHz
6000 MHz
7500 MHz
8000 MHz
10 Hz-9 kHz
3000 MHz
6000 MHz
7500 MHz
8000 MHz
10 Hz-9 kHz
3000 MHz
6000 MHz
7500 MHz
8000 MHz
10 Hz-9 kHz
3000 MHz
6000 MHz
7500 MHz
8000 MHz
50% CTRL to 0.05dB final value (-40 to 85 ºC)
Rising Edge
50% CTRL to 0.05dB final value (-40 to 85 ºC)
Falling Edge
50% CTRL to 90% or 10% RF
All bands @ 1:1 VSWR, 100% duty cycle
8000 MHz
8000 MHz
31
70
40
34
27
25
74
40
28
24
21
Condition
Min
10 Hz
1
0.7
0.8
1.0
1.1
1.2
80
45
39
32
31
84
45
33
29
27
24
23
18
14
13
35
18
13
11
10
14
15
5
33
58
100
18
45
8
Typ
Max
8 GHz
1.0
1.1
1.3
1.5
1.6
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
μs
μs
μs
dBm
dBm
dBm
Unit
RFC-RFX Insertion Loss
RFX-RFX Isolation
RFC-RFX Isolation
Return Loss (RFC to active port)
Return Loss (terminated port)
Settling Time
Switching Time (T
SW
)
P1dB
1
Input 1 dB Compression
RFX-RFC
Input IP3
Input IP2
Note 1: Maximum Operating Pin (50Ω) is shown in
Table 3.
Please refer to
Figures 4, 5,
and
6
when operating the part at low frequency
©2010-2012 Peregrine Semiconductor Corp. All rights reserved.
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Document No. 70-0299-09
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UltraCMOS
®
RFIC Solutions
Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com
PE42540
Product Specification
Figure 3. Pin Configuration (Top View)
Vss
EXT
GND
GND
GND
GND
V1
V
DD
V2
Table 3. Operating Ranges
Parameter
V
DD
Supply Voltage
Vss
EXT
Negative Power Supply
Voltage
1
Iss Negative Supply Current
I
DD
Power Supply Current
V
DD
= 3.3V, Vss
EXT
= 0V,
Temp = 85°C
I
DD
Power Supply Current
V
DD
= 3.6V, Vss
EXT
used
V
CTRL
Control Voltage High
V
CTRL
Control Voltage Low
I
CTRL
Control Current
P
IN
Thru Path
2
(50Ω, RF Power in)
9 kHz - 8 GHz
P
max
Max power into termination
(50Ω)
9 kHz
≤
6 MHz
2,3
6 MHz - 8 GHz
2,3
P
max
Max power, hot switching (50Ω)
9 kHz
≤
6 MHz
2,3
6 MHz - 8 GHz
2,3
T
OP
Operating temperature range
Notes:
Min
3.0
-3.6
Typ
3.3
-3.3
-10
90
Max
3.55
-3.0
-40
160
50
Unit
V
V
µA
µA
µA
V
V
µA
1.2
0
1.5
0
V
DD
0.4
1
figs.
4,5,6
figs.
4,5,6
20
figs.
4,5,6
20
GND
GND
GND
GND
RFC
GND
GND
GND
Table 2. Pin Descriptions
Pin #
1, 3-6, 8,
9-12, 14-17,
19-22, 24-26,
28, 32
2
7
13
18
23
27
29
30
31
Paddle
Notes:
dBm
Pin Name
Description
dBm
°C
GND
Ground
-40
+85
RF4
2
RF I/O
RF I/O
RF Common
RF I/O
RF I/O
Supply
Switch control input, CMOS logic level
Switch control input, CMOS logic level
External Vss Negative Voltage
Control
Exposed solder pad: Ground for
proper operation
RF2
2
RFC
2
RF1
2
RF3
2
V
DD
V1
V2
Vss
EXT1
GND
1. Applies only when external Vss power supply is used. Otherwise,
Vss
EXT
= 0
2. 100% duty cycle (-40 to +85° C, 1:1 VSWR)
3. Do not exceed 20 dBm
1. Use Vss
EXT
(pin 31, Vss
EXT
= -V
DD
) to bypass and disable internal
negative voltage generator. Connect Vss
EXT
(pin 31) to GND
(Vss
EXT
= 0V) to enable internal negative voltage generator
2. All RF pins must be DC blocked with an external series capacitor
or held at 0 VDC
Document No. 70-0299-09
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©2010-2012 Peregrine Semiconductor Corp. All rights reserved.
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Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com
PE42540
Product Specification
Table 4. Absolute Maximum Ratings
Parameter/Condition
T
ST
Storage temperature range
V
DD
Supply Voltage
V
CTRL
Control Voltage, V1 and V2
P
IN
Thru Path (50Ω, RF Power in)
9 kHz - 8 GHz
P
max
Max power into termination (50Ω)
9 kHz
≤
6 MHz
1
6 MHz - 8 GHz
V
ESD
ESD Voltage HBM
RFC
All Pins
2
Switching Frequency
Max
+150
4
4
figs.
4,5,6
figs.
4,5,6
20
2000
1000
100
Unit
°C
V
V
Min
-60
-0.3
The PE42540 has a maximum 25 kHz switching
rate when the internal negative voltage generator
is used (pin 31 = GND). The rate at which the
PE42540 can be switched is only limited to the
switching time (Table
1)
if an external negative
supply is provided at (pin 31 = Vss
EXT
).
Optional External Vss Control (Vss
EXT
)
dBm
V
V
V
V
ESD
ESD Voltage MM, all pins
3
Notes: 1. Do not exceed 20 dBm
2. HBM, MIL-STD 883 Method 3015.7
3. MM JEDEC JESD22-A115-A
For proper operation, the Vss
EXT
control pin must
be grounded or tied to the Vss voltage specified
in
Table 3.
When the Vss
EXT
control pin is
grounded, FETs in the switch are biased with an
internal voltage generator. For applications that
require the lowest possible spur performance,
Vss
EXT
can be applied externally to bypass the
internal negative voltage generator.
Spurious Performance
The typical spurious performance of the PE42540
is -144 dBm when Vss
EXT
= 0V (pin 31 = GND). If
further improvement is desired, the internal
negative voltage generator can be disabled by
setting Vss
EXT
= -V
DD
.
Table 5. Truth Table
State
RF1 on
RF2 on
RF3 on
RF4 on
V1
0
1
0
1
V2
0
0
1
1
Exceeding absolute maximum ratings may cause
permanent damage. Operation should be
restricted to the limits in the Operating Ranges
table. Operation between operating range
maximum and absolute maximum for extended
periods may reduce reliability.
Electrostatic Discharge (ESD) Precautions
When handling this UltraCMOS
®
device, observe
the same precautions that you would use with
other ESD-sensitive devices. Although this device
contains circuitry to protect it from damage due to
ESD, precautions should be taken to avoid
exceeding the specified rating.
Latch-Up Avoidance
Unlike conventional CMOS devices, UltraCMOS
®
devices are immune to latch-up.
Moisture Sensitivity Level
The Moisture Sensitivity Level rating for the
PE42540 in the 32-lead 5x5 mm LGA package is
MSL3.
©2010-2012 Peregrine Semiconductor Corp. All rights reserved.
Page 4 of 12
Document No. 70-0299-09
|
UltraCMOS
®
RFIC Solutions
Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com
PE42540
Product Specification
Low Frequency Operation
Table 6
shows the minimum and maximum
voltage limits when operating the device under
various V
DD
and Vss
EXT
voltage conditions below
9 kHz. Refer to
Figures 4, 5,
and
6
to determine
the maximum operating power over the frequency
range of the device.
Table 6. Instantaneous RF Pin Voltage Limits
for Operation Below 9 kHz
V
DD
≥
3.0
3.0
3.3
3.5
3.6
Vss
EXT
0.0
-3.0
-3.3
-3.5
-3.6
Minimum Peak
Voltage at RF Port
-0.2
-0.6
-0.3
-0.1
0.0
Maximum Peak
Voltage at RF Port
1.2
1.6
1.3
1.1
1.0
Maximum Operating Power vs. Frequency
Figures 4, 5,
and
6
show the power limit of the
device will increase with frequency. As the
frequency increases, the contours and maximum
power limit will increase as shown in the curves.
Document No. 70-0299-09
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©2010-2012 Peregrine Semiconductor Corp. All rights reserved.
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Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com
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