K6F4008U1D Family
Document Title
CMOS SRAM
512K x8 bit Super Low Power and Low Voltage Full CMOS Static RAM
Revision History
Revision No. History
0.0
1.0
Initial draft
Finalized
- Change for tWHZ: 25 to 20ns for 70ns product
- Change for tDW: 20 to 25ns for 55ns product
25 to 30ns for 70ns product
Draft Date
March 16, 2000
April 24, 2000
Remark
Preliminary
Final
The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and
products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices.
-1-
Revision 1.0
April 2000
K6F4008U1D Family
FEATURES
•
•
•
•
•
•
CMOS SRAM
GENERAL DESCRIPTION
The K6F4008U1D families are fabricated by SAMSUNG′s
advanced full CMOS process technology. The families support
small package type for user flexibility of system design. The
families also supports low data retention voltage for battery
back-up operation with low data retention current.
512K x 8 bit Super Low Power and Low Voltage Full CMOS Static RAM
Process Technology: Full CMOS
Organization: 512K x8 bit
Power Supply Voltage: 2.7~3.3V
Low Data Retention Voltage: 1.5V(Min)
Three state output status and TTL Compatible
Package Type: 32-TSOP1-0813.4F
PRODUCT FAMILY
Power Dissipation
Product Family
Operating Temperature
Vcc Range
Speed
Standby
(I
SB1
, Typ.)
0.5µA
Operating
(I
CC1
, Max)
3mA
PKG Type
K6F4008U1D-F
Industrial(-40~85°C)
2.7~3.3V
55
1)
/70ns
32-TSOP1-0813.4F
1. The parameter is measured with 30pF test load.
PIN DESCRIPTION
A11
A9
A8
A13
WE
A18
A15
VCC
A17
A16
A14
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
A10
CS
I/O8
I/O7
I/O6
I/O5
I/O4
VSS
I/O3
I/O2
I/O1
A0
A1
A2
A3
FUNCTIONAL BLOCK DIAGRAM
Clk gen.
Precharge circuit.
32-
S
TSOP1
(Forward)
Row
Address
Row
select
Memory array
2048 rows
256×8 columns
Name
CS
WE
OE
Function
Chip Select Input
Write Enable Input
Name
Vcc
Vss
Function
Power
Ground
I/O
1
I/O
8
Data
cont
I/O Circuit
Column select
Output Enable Input I/O
1
~I/O
8
Data Inputs/Outputs
A
0
~A
18
Address Inputs
Data
cont
Column Address
CS
WE
OE
Control
logic
SAMSUNG ELECTRONICS CO., LTD.
reserves the right to change products and specifications without notice
.
-2-
Revision 1.0
April 2000
K6F4008U1D Family
PRODUCT LIST
Industrial Temperature Products(-40~85°C)
Part Name
K6F4008U1D-YF55
K6F4008U1D-YF70
Function
CMOS SRAM
32-sTSOP1-F, 55ns, 3.0V
32-sTSOP1-F, 70ns, 3.0V
FUNCTIONAL DESCRIPTION
CS
H
L
L
L
OE
X
1)
H
L
X
1)
WE
X
1)
H
H
L
I/O
High-Z
High-Z
Dout
Din
Mode
Deselected
Output Disabled
Read
Write
Power
Standby
Active
Active
Active
1. X means don′t care (Must be in low or high state)
ABSOLUTE MAXIMUM RATINGS
1)
Item
Voltage on any pin relative to Vss
Voltage on Vcc supply relative to Vss
Power Dissipation
Storage temperature
Operating Temperature
Symbol
V
IN
,V
OUT
V
CC
P
D
T
STG
T
A
Ratings
-0.2 to V
CC
+0.5V
-0.2 to 4.0V
1.0
-65 to 150
-40 to 85
Unit
V
V
W
°C
°C
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be
restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
-3-
Revision 1.0
April 2000
K6F4008U1D Family
RECOMMENDED DC OPERATING CONDITIONS
1)
Item
Supply voltage
Ground
Input high voltage
Input low voltage
Note:
1. T
A
=-40 to 85°C, otherwise specified.
2. Overshoot: Vcc+2.0V in case of pulse width
≤20ns.
3. Undershoot: -2.0V in case of pulse width
≤20ns.
4. Overshoot and undershoot are sampled, not 100% tested.
CMOS SRAM
Symbol
Vcc
Vss
V
IH
V
IL
Min
2.7
0
2.2
-0.2
3)
Typ
3.0
0
-
-
Max
3.3
0
Vcc+0.3
2)
0.6
Unit
V
V
V
V
CAPACITANCE
1)
(f=1MHz, T
A
=25°C)
Item
Input capacitance
Input/Output capacitance
1. Capacitance is sampled, not 100% tested.
Symbol
C
IN
C
IO
Test Condition
V
IN
=0V
V
IO
=0V
Min
-
-
Max
8
10
Unit
pF
pF
DC AND OPERATING CHARACTERISTICS
Item
Input leakage current
Output leakage current
Operating power supply current
Average operating current
Output low voltage
Output high voltage
Standby Current(TTL)
Standby Current (CMOS)
Symbol
I
LI
I
LO
I
CC
I
CC1
I
CC2
V
OL
V
OH
I
SB
I
SB1
V
IN
=Vss to Vcc
CS=V
IH,
OE=V
IH
or WE=V
IL
, V
IO
=Vss to Vcc
I
IO
=0mA, CS=V
IL,
WE=V
IH,
V
IN
=V
IL
or V
IH
Cycle time=1µs, 100%duty, I
IO
=0mA, CS≤0.2V, V
IN
≤0.2V
or V
IN
≥V
CC
-0.2V
Test Conditions
Min Typ Max Unit
-1
-1
-
-
-
-
2.4
-
-
-
-
-
-
-
-
-
-
0.5
1
1
2
3
30
0.4
-
0.3
12
1)
µA
µA
mA
mA
mA
V
V
mA
µA
Cycle time=Min, I
IO
=0mA, 100% duty, CS=V
IL
, VIN=V
IL
or V
IH
I
OL
= 2.1mA
I
OH
= -1.0mA
CS=V
IH
, Other inputs=V
IL
or V
IH
CS≥Vcc-0.2V, Other input =0~Vcc
1. Super low power product=5µA with special handling.
-4-
Revision 1.0
April 2000
K6F4008U1D Family
AC OPERATING CONDITIONS
TEST CONDITIONS
(Test Load and Test Input/Output Reference)
Input pulse level: 0.4 to 2.2V
Input rising and falling time: 5ns
Input and output reference voltage: 1.5V
Output load (See right): C
L
= 100pF+1TTL
C
L
=30pF+1TTL
CMOS SRAM
V
TM
3)
R
1
2)
C
L
1)
R
2
2)
1. Including scope and jig capacitance
2. R
1
=3070Ω
,
R
2
=3150Ω
3. V
TM
=2.8V
AC CHARACTERISTICS
(Vcc=2.7~3.3V, Industrial product:T
A
=-40 to 85°C)
Speed Bins
Parameter List
Symbol
Min
Read Cycle Time
Address Access Time
Chip Select to Output
Output Enable to Valid Output
Read
Chip Select to Low-Z Output
Output Enable to Low-Z Output
Chip Disable to High-Z Output
Output Disable to High-Z Output
Output Hold from Address Change
Write Cycle Time
Chip Select to End of Write
Address Set-up Time
Address Valid to End of Write
Write
Write Pulse Width
Write Recovery Time
Write to Output High-Z
Data to Write Time Overlap
Data Hold from Write Time
End Write to Output Low-Z
t
RC
t
AA
t
CO
t
OE
t
LZ
t
OLZ
t
HZ
t
OHZ
t
OH
t
WC
t
CW
t
AS
t
AW
t
WP
t
WR
t
WHZ
t
DW
t
DH
t
OW
55
-
-
-
10
5
0
0
10
55
45
0
45
40
0
0
25
0
5
55ns
Max
-
55
55
25
-
-
20
20
-
-
-
-
-
-
-
20
-
-
-
Min
70
-
-
-
10
5
0
0
10
70
60
0
60
50
0
0
30
0
5
70ns
Max
-
70
70
35
-
-
25
25
-
-
-
-
-
-
-
20
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Units
DATA RETENTION CHARACTERISTICS
Item
Vcc for data retention
Data retention current
Data retention set-up time
Recovery time
Symbol
VDR
IDR
tSDR
tRDR
Test Condition
CS≥Vcc-0.2V
Vcc=1.5V, CS≥Vcc-0.2V
See data retention waveform
Min
1.5
-
0
tRC
Typ
-
0.5
-
-
Max
3.3
3
1)
-
-
Unit
V
µA
ns
1. Super low power product=2µA with special handling.
-5-
Revision 1.0
April 2000
Analog electronics
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