NC7SZ74 — TinyLogic
®
UHS D-Type Flip-Flow with Preset and Clear
August 2011
NC7SZ74
TinyLogic
®
UHS D-Type, Flip-Flop with Preset and
Clear
Features
Ultra-High Speed: t
PD
2.6ns (Typical) into 50pF at
5V V
CC
High Output Drive: ±24mA at 3V V
CC
Broad V
CC
Operating Range: 1.65V to 5.5V
Power Down High-Impedance Inputs/Outputs
Over-Voltage Tolerance Inputs Facilitate 5V to 3V
Translation
Proprietary Noise/EMI Reduction Circuitry
Ultra-Small MicroPak™ Package
Space-Saving US8 Surface Mount Package
Description
The NC7SZ74 is a single, D-type, CMOS flip-flop with
preset and clear from Fairchild’s ultra high-speed series
®
of TinyLogic . The device is fabricated with advanced
CMOS technology to achieve ultra high speed with high
output drive, while maintaining low static power
dissipation over a very broad V
CC
operating range of
1.65V to 5.5V V
CC
. The inputs and outputs are high
impedance when V
CC
is 0V. Inputs tolerate voltages up
to 7V, independent of V
CC
operating voltage.
The signal level applied to the D input is transferred to
the Q output during the positive-going transition of the
CLK pulse.
Ordering Information
Part Number
NC7SZ74K8X
NC7SZ74L8X
Top Mark
SZ74
N9
Package
8-Lead US8, JEDEC MO-187, Variation CA 3.1mm Wide-
8-Lead MicroPak, 1.6 mm Wide
Packing Method
3000 Units on
Tape & Reel
5000 Units on
Tape & Reel
© 2001 Fairchild Semiconductor Corporation
NC7SZ74 • Rev. 1.0.2
www.fairchildsemi.com
NC7SZ74 — TinyLogic
®
UHS D-Type Flip-Flop with Preset and Clear
Connection Diagrams
IEEE/IEC
Figure 1. Logic Symbol
Pin Configurations
Figure 2. US8 (Top View)
Figure 3. MicroPak™ (Top Through View)
Pin Definitions
Pin # US8
1
2
3
4
5
6
7
8
Pin # MicroPak
7
6
5
4
3
2
1
8
Name
CK
D
/Q
GND
Q
/CLR
/PR
V
CC
Description
Clock Pulse Input
Data Input
Flip-Flop Output
Ground
Flip-Flop Output
Direct Clear Input
Direct Preset Input
Supply Voltage
Function Table
Inputs
/CLR
L
H
L
H
H
H
Output
D
X
X
X
L
H
X
/PR
H
L
L
H
H
H
CK
X
X
X
Q
L
H
H
L
H
Q
n
X = Immaterial
= Rising Edge
/Q
H
L
H
H
L
/Q
n
½Falling
Edge
Function
Clear
Preset
No Change
H = HIGH Logic Level
L = LOW Logic Level
Qn = No change in data
Z = High Impedance
© 2001 Fairchild Semiconductor Corporation
NC7SZ74 • Rev. 1.0.2
www.fairchildsemi.com
2
NC7SZ74 — TinyLogic
®
UHS D-Type Flip-Flop with Preset and Clear
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
V
CC
V
IN
V
OUT
I
IK
I
OK
I
OUT
I
CC
or I
GND
T
STG
T
J
T
L
P
D
ESD
Supply Voltage
DC Input Voltage
DC Output Voltage
DC Input Diode Current
DC Output Diode Current
Parameter
Min.
-0.5
-0.5
-0.5
Max.
7.0
7.0
7.0
-50
-50
±50
±50
Unit
V
V
V
mA
mA
mA
mA
°C
°C
°C
mW
V
V
IN
< 0V
V
OUT
< 0V
DC Output Source/Sink Current
DC V
CC
or Ground Current
Storage Temperature Range
Junction Temperature Under Bias
Junction Lead Temperature (Soldering, 10 Seconds)
Power Dissipation at +85°C
Human Body Model, JEDEC:JESD22-A114
Charge Device Model: JEDEC:JESD22-C101
-65
+150
+150
+260
250
5000
2000
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
V
CC
V
IN
V
OUT
Parameter
Supply Voltage Operating
Supply Voltage Data Retention
Input Voltage
Output Voltage
Conditions
Min.
1.65
1.50
0
Max.
5.50
5.50
5.5
V
CC
5.5
20
10
5
+85
250
280
Unit
V
V
V
Active State
3-State
V
CC
=1.8V, 2.5V ± 0.2V
V
CC
=3.3V ± 0.3V
V
CC
=5.0V ± 0.5V
0
0
0
0
0
-40
t
r
, t
f
T
A
JA
Input Rise and Fall Times
Operating Temperature
Thermal Resistance
ns/V
°C
°C/W
US8
MicroPak™-8
Note:
1. Unused inputs must be held HIGH or LOW. They may not float.
© 2001 Fairchild Semiconductor Corporation
NC7SZ74 • Rev. 1.0.2
www.fairchildsemi.com
3
NC7SZ74 — TinyLogic
®
UHS D-Type Flip-Flop with Preset and Clear
DC Electrical Characteristics
Symbol
V
IH
V
IL
Parameter
HIGH Level Control
Input Voltage
LOW Level Control
Input Voltage
V
CC
1.65 to 1.95
2.30 to 5.50
1.65 to 1.95
2.30 to 5.50
1.65
2.30
3.00
4.50
Conditions
T
A
=+25°C
Min.
0.75V
CC
0.70V
CC
0.25V
CC
0.30V
CC
1.55
1.65
2.30
3.00
4.50
1.52
2.15
2.80
2.68
4.20
0.10
0.10
0.10
0.10
0.80
0.10
0.15
0.22
0.22
0.24
0.30
0.40
0.55
0.55
±0.1
1
1
T
A
=-40 to +85°C
Max.
Min.
0.75V
CC
0.70V
CC
0.25V
CC
0.30V
CC
1.55
2.20
2.90
4.40
1.29
1.90
2.40
2.30
3.80
0.10
0.10
0.10
0.10
0.24
0.30
0.40
0.55
0.55
±1.0
10
10
Typ.
Max.
Units
V
V
V
IN
=V
IH
,
I
OH
=-100µA
2.20
2.90
4.40
1.29
1.90
2.40
2.30
3.80
V
OH
HIGH Level Output
Voltage
1.65
2.30
3.00
3.00
4.50
1.65
2.30
3.00
4.50
I
OH
=-4mA
I
OH
=-8mA
I
OH
=-16mA
I
OH
=-24mA
I
OH
=-32mA
V
V
IN
=V
IH
,
I
OL
=100µA
V
OL
LOW Level Control
Output Voltage
1.65
2.30
3.00
3.00
4.50
I
OL
=4mA
I
OL
=8mA
I
OL
=16mA
I
OL
=24mA
I
OL
=32mA
V
IN
5.5V
V
IN
or V
OUT
=5.5V
V
I
IN
I
OFF
I
CC
Input Leakage
Current
Power Off Leakage
Current
Quiescent Supply
Current
0 to 5.5
0
µA
µA
µA
1.65 to 5.50 V
IN
=5.5V, GND
© 2001 Fairchild Semiconductor Corporation
NC7SZ74 • Rev. 1.0.2
www.fairchildsemi.com
4
AC Electrical Characteristics
Symbol
Parameter
V
CC
1.80 ± 0.15
2.50 ± 0.20
f
MAX
Maximum Clock
Frequency
3.30 ± 0.30
5.00 ± 0.50
3.30 ± 0.50
5.00 ± 0.50
1.80 ± 0.15
2.50 ± 0.20
t
PLH
, t
PHL
Propagation Delay
CK to Q, /Q
3.30 ± 0.30
5.00 ± 0.50
3.30 ± 0.30
5.00 ± 0.50
1.80 ± 0.15
2.50 ± 0.20
t
PLH
, t
PHL
Propagation Delay
/CLR, /PR to Q, /Q
3.30 ± 0.30
5.00 ± 0.50
3.30 ± 0.30
5.00± 0.50
1.80 ± 0.15
2.50 ± 0.20
3.30 ± 0.30
t
S
Setup Time CK to D
5.00 ± 0.50
3.30 ± 0.30
5.00± 0.50
1.80 ± 0.15
2.50 ± 0.20
3.30 ± 0.30
t
H
Hold Time, CK to D
5.00 ± 0.50
3.30 ± 0.30
5.00± 0.50
1.80 ± 0.15
2.50 ± 0.20
t
W
Pulse Width, CK,
/PR, /CLR
3.30 ± 0.30
5.00 ± 0.50
3.30 ± 0.30
5.00± 0.50
1.80 ± 0.15
2.50 ± 0.20
t
REC
Recover Time /CLR,
/PR to CK
3.30 ± 0.30
5.00 ± 0.50
3.30 ± 0.30
5.00 ± 0.50
C
L
=50pF,
R
D
=500
S
1
=Open
C
L
=15pF,
R
L
=1M
S
1
=Open
C
L
=50pF,
R
D
=500
S
1
=Open
C
L
=15pF,
R
L
=1M
S
1
=Open
C
L
=50pF,
R
D
=500
S
1
=Open
C
L
=15pF,
R
L
=1M
S
1
=Open
C
L
=50pF,
R
D
=500
S
1
=Open
C
L
=15pF,
R
L
=1M
S
1
=Open
C
L
=50pF,
R
D
=500
S
1
=Open
C
L
=15pF,
R
L
=1M
S
1
=Open
C
L
=50pF
R
D
=500,
S
1
=Open
C
L
=15pF,
R
D
=1M
S
1
=Open
C
L
=50pF
R
D
=500,
S
1
=Open
C
L
=15pF
R
D
=1M
S
1
=Open
NC7SZ74 — TinyLogic
®
UHS D-Type Flip-Flop with Preset and Clear
Conditions
T
A
=+25°C
Min.
75
150
200
250
175
200
2.5
1.5
1.0
0.8
1.0
1.0
2.5
1.5
1.0
0.8
1.0
1.0
6.5
3.5
2.0
1.5
2.0
1.5
0.5
0.5
0.5
0.5
0.5
0.5
6.0
4.0
3.0
2.0
3.0
2.0
8.0
4.5
3.0
3.0
3.0
3.0
6.5
3.8
2.8
2.2
3.4
2.6
6.5
3.8
2.8
2.2
3.4
2.6
12.5
7.5
6.5
4.5
7.0
5.0
14.0
9.0
6.5
5.0
7.0
5.0
T
A
=-40 to +85°C
Max.
Min.
75
150
200
250
175
200
2.5
1.5
1.0
0.8
1.0
1.0
2.5
1.5
1.0
0.8
1.0
1.0
6.5
3.5
2.0
1.5
2.0
1.5
0.5
0.5
0.5
0.5
0.5
0.5
6.0
4.0
3.0
2.0
3.0
2.0
8.0
4.5
3.0
3.0
3.0
3.0
13.0
8.0
7.0
5.0
7.5
5.5
14.5
9.5
7.0
5.5
7.5
5.5
Typ.
Max.
Units
Figure
Figure 4
Figure 8
ns
Figure 4
Figure 6
ns
Figure 4
Figure 6
ns
Figure 4
Figure 7
ns
Figure 4
Figure 7
ns
Figure 4
Figure 8
ns
Figure 4
Figure 7
Continued on the following page…
© 2001 Fairchild Semiconductor Corporation
NC7SZ74 • Rev. 1.0.2
www.fairchildsemi.com
5
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