Burr-Brown Products
from Texas Instruments
PCM1850
PCM1851
SLES108
−
MARCH 2004
24-BIT, 96-kHz STEREO A/D CONVERTER
WITH 6
y
2-CHANNEL MUX AND PGA
FEATURES
D
Multiplexer and Programmable-Gain Amplifier
(PGA)
−
6×2-Channel Single-Ended Inputs
−
Multiplexed Output
−
Maximum Input Level: 2.4 V rms
−
Input Resistance: 50 kΩ, Minimum
−
PGA Gain: 11 to –11 dB Range,
0.5 dB/Step
−
Master/Slave Mode Selectable
−
Data Formats: 24-Bit Left Justified,
24-Bit I
2
S, 16-, 24-Bit Right Justified
Mode Control by Serial Interface:
−
With SPI Control (PCM1850)
−
With I
2
C Control (PCM1851)
Sampling Rate: 16–96 kHz
System Clock: 256 f
s
, 384 f
s
, 512 f
s
, 768 f
s
Dual Power Supplies:
5 V for Analog, 3.3 V for Digital
Package: 32-Pin TQFP
D
D
D
D
D
24-Bit Delta-Sigma Stereo A/D Converter
D
Antialiasing Filter Included
D
Oversampling Decimation Filter
−
−
−
−
D
D
Lead-Free Product
Oversampling Frequency:
×64
Pass-Band Ripple:
±0.05
dB
Stop-Band Attenuation: –65 dB
On-Chip High-Pass Filter: 0.91 Hz (48 kHz)
D
High Performance
−
THD+N: 0.0023% (Typically)
−
SNR: 101 dB (Typically)
−
Dynamic Range: 102 dB (Typically)
D
PCM Audio Interface
DESCRIPTION
APPLICATIONS
D
DVD/HDD/DVD+HDD Recorder
D
AV Amplifier Receiver
D
CD Recorder
D
MD Recorder
D
Multi-Track Recorder
D
Electric Musical Instrument
The PCM1850/1851 is a high-performance, low-cost, single-chip stereo analog-to-digital converter with a single-ended
analog front end that consists of a 6-stereo-input multiplexer and wide-range PGA. The PCM1850/1851 includes a
delta-sigma modulator with 64-times oversampling, a digital decimation filter and a low-cut filter that removes the dc
component of the input signal. For various applications, the PCM1850/1851 supports two modes (master and slave) and
four data formats through a serial control interface, SPI for the PCM1850 and I
2
C for the PCM1851, respectively. The
PCM1850/1851 is suitable for a wide variety of cost-sensitive DVD/CD/MD recorder and receiver applications where good
performance and operation from a 5-V analog supply and 3.3-V digital supply is required. The PCM1850/1851 is fabricated
using a highly advanced CMOS process and is available in a small 32-pin TQFP package.
ORDERING INFORMATION
PRODUCT
PACKAGE
PACKAGE CODE
OPERATION
TEMPERATURE
RANGE
–40°C to 85°C
40°C
–40°C to 85°C
40°C
PACKAGE
MARKING
PCM1850
PCM1851
ORDERING
NUMBER
PCM1850PJT
PCM1850PJTR
PCM1851PJT
PCM1851PJTR
TRANSPORT
MEDIA
Tray
Tape and reel
Tray
Tape and reel
PCM1850PJT
PCM1851PJT
32-Lead
32 Lead TQFP
32-Lead
32 Lead TQFP
32PJT
32PJT
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products
conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters.
Copyright
©
2004, Texas Instruments Incorporated
PCM1850
PCM1851
SLES108
−
MARCH 2004
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate
precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to
damage because very small parametric changes could cause the device not to meet its published specifications.
BLOCK DIAGRAM
V
IN
L1
V
IN
L2
V
IN
L3
V
IN
L4
V
IN
L5
V
IN
L6
MOUTL
V
REF
1
V
REF
S
V
REF
2
V
IN
R1
V
IN
R2
V
IN
R3
V
IN
R4
V
IN
R5
V
IN
R6
MOUTR
Reference
Single-Ended
MUX and PGA
Delta-Sigma
Modulator
BCK
LRCK
DOUT
Audio
Data
Interface
Decimation
Filter
with
High-Pass Filter
OVER
Control
Data
Interface
MS (ADR)
(1)
MD (SDA)
(1)
MC (SCL)
(1)
TEST0
TEST1
Single-Ended
MUX and PGA
Delta-Sigma
Modulator
Power Supply
Clock and Timing Control
RST
SCKI
V
CC
(1)
AGND DGND
V
DD
PCM1850 (PCM1851)
PIN ASSIGNMENTS
PCM1850
(TOP VIEW)
PCM1851
(TOP VIEW)
V
IN
R6
V
IN
L6
V
IN
R5
V
IN
L5
V
IN
R4
V
IN
L4
V
IN
R3
V
IN
L3
24 23 22 21 20 19 18 17
V
REF
S
V
REF
1
V
REF
2
V
cc
AGND
MS
MC
MD
25
26
27
28
29
30
31
32
1
2 3 4
5 6 7 8
16
15
14
13
12
11
10
9
V
IN
R2
V
IN
L2
V
IN
R1
V
IN
L1
MOUTL
MOUTR
RST
TEST1
V
REF
S
V
REF
1
V
REF
2
V
cc
AGND
ADR
SCL
SDA
V
IN
R6
V
IN
L6
V
IN
R5
V
IN
L5
V
IN
R4
V
IN
L4
V
IN
R3
V
IN
L3
24 23 22 21 20 19 18 17
25
26
27
28
29
30
31
32
1 2
3 4 5 6
7 8
16
15
14
13
12
11
10
9
V
IN
R2
V
IN
L2
V
IN
R1
V
IN
L1
MOUTL
MOUTR
RST
TEST1
LRCK
BCK
DOUT
OVER
DGND
V
DD
SCKI
TEST0
2
LRCK
BCK
DOUT
OVER
DGND
V
DD
SCKI
TEST0
www.ti.com
PCM1850
PCM1851
SLES108
−
MARCH 2004
Terminal Functions
PCM1850
TERMINAL
NAME
AGND
BCK
DGND
DOUT
LRCK
MC
MD
MOUTL
MOUTR
MS
OVER
RST
SCKI
TEST0
TEST1
V
CC
V
DD
V
IN
L1
V
IN
L2
V
IN
L3
V
IN
L4
V
IN
L5
V
IN
L6
V
IN
R1
V
IN
R2
V
IN
R3
V
IN
R4
V
IN
R5
V
IN
R6
V
REF
S
V
REF
1
V
REF
2
(1)
(2)
PIN
29
2
5
3
1
31
32
12
11
30
4
10
7
8
9
28
6
13
15
17
19
21
23
14
16
18
20
22
24
25
26
27
I/O
—
I/O
—
O
I/O
I
I
O
O
I
O
I
I
I
I
—
—
I
I
I
I
I
I
I
I
I
I
I
I
—
—
—
Analog GND
Bit clock input/output
(1)
Digital GND
Audio data output
Sampling clock input/output
(1)
Mode control clock input
(2)
Mode control data input
(2)
Multiplexer output, L-channel
Multiplexer output, R-channel
Mode control select input
(3)
Overflow flag
Reset, active LOW
(3)
DESCRIPTIONS
System clock input; 256 f
S
, 384 f
S
, 512 f
S
or 768 f
S(2)
Test 0, must be connected to GND
(3)
Test 1, must be connected to GND
(3)
Analog power supply, 5-V
Digital power supply, 3.3-V
Analog input 1, L-channel
Analog input 2, L-channel
Analog input 3, L-channel
Analog input 4, L-channel
Analog input 5, L-channel
Analog input 6, L-channel
Analog input 1, R-channel
Analog input 2, R-channel
Analog input 3, R-channel
Analog input 4, R-channel
Analog input 5, R-channel
Analog input 6, R-channel
Reference S decoupling capacitor (= 0.5 V
CC
)
Reference 1 decoupling capacitor (= 0.5 V
CC
)
Reference 2 decoupling capacitor (= V
CC
)
Schmitt-trigger input with internal pulldown resistor (50 kΩ, typically)
Schmitt-trigger input, 5-V tolerant
(3)
Schmitt-trigger input with internal pulldown resistor (50 kΩ, typically), 5-V tolerant
3
PCM1850
PCM1851
SLES108
−
MARCH 2004
www.ti.com
Terminal Functions
PCM1851
TERMINAL
NAME
ADR
AGND
BCK
DGND
DOUT
LRCK
MOUTL
MOUTR
OVER
RST
SCKI
SCL
SDA
TEST0
TEST1
V
CC
V
DD
V
IN
L1
V
IN
L2
V
IN
L3
V
IN
L4
V
IN
L5
V
IN
L6
V
IN
R1
V
IN
R2
V
IN
R3
V
IN
R4
V
IN
R5
V
IN
R6
V
REF
S
V
REF
1
V
REF
2
(1)
(2)
PIN
30
29
2
5
3
1
12
11
4
10
7
31
32
8
9
28
6
13
15
17
19
21
23
14
16
18
20
22
24
25
26
27
I/O
I
—
I/O
—
O
I/O
O
O
O
I
I
I
I/O
I
I
—
—
I
I
I
I
I
I
I
I
I
I
I
I
—
—
—
Mode control address select input
(1)
Analog GND
Bit clock input/output
(2)
Digital GND
Audio data output
Sampling clock input/output
(2)
Multiplexer output, L-channel
Multiplexer output, R-channel
Overflow flag
Reset, active LOW
(1)
DESCRIPTIONS
System clock input; 256 f
S
, 384 f
S
, 512 f
S
or 768 f
S(3)
Mode control clock input
(3)
Mode control data input/output
(4)
Test 0, must be connected to GND
(1)
Test 1, must be connected to GND
(1)
Analog power supply, 5-V
Digital power supply, 3.3-V
Analog input 1, L-channel
Analog input 2, L-channel
Analog input 3, L-channel
Analog input 4, L-channel
Analog input 5, L-channel
Analog input 6, L-channel
Analog input 1, R-channel
Analog input 2, R-channel
Analog input 3, R-channel
Analog input 4, R-channel
Analog input 5, R-channel
Analog input 6, R-channel
Reference S decoupling capacitor (= 0.5 V
CC
)
Reference 1 decoupling capacitor (= 0.5 V
CC
)
Reference 2 decoupling capacitor (= V
CC
)
Schmitt-trigger input with internal pulldown resistor (50 kΩ, typically), 5-V tolerant
Schmitt-trigger input with internal pulldown resistor (50 kΩ, typically)
(3)
Schmitt-trigger input, 5-V tolerant
(4)
Schmitt-trigger input/open-drain LOW output, 5-V tolerant
4
www.ti.com
PCM1850
PCM1851
SLES108
−
MARCH 2004
ABSOLUTE MAXIMUM RATINGS
Supply voltage: V
CC
Supply voltage: V
DD
Ground voltage differences: AGND, DGND
over operating free-air temperature range unless otherwise noted
(1)
–0.3 V to 6.5 V
–0.3 V to 4 V
±0.1
V
–0.3 V to (V
DD
+ 0.3 V) < 4 V
–0.3 V to 6.5 V
–3 V to (V
CC
+ 3 V) < 9 V
–0.3 V to (V
CC
+ 0.3 V) < 6.5 V
±10
mA
–40°C to 125°C
–55°C to 150°C
150°C
260°C, 5 s
260°C
Digital input voltage: LRCK, BCK, DOUT, OVER
Digital input voltage: RST, SCKI, MS (ADR)
(2)
, MC (SCL)
(2)
, MD (SDA)
(2)
, TEST0, TEST1
Analog input voltage: V
IN
L1–6, V
IN
R1–6
Analog input voltage: MOUTL, MOUTR, V
REF
1, V
REF
2, V
REF
S
Input current (any pins except supplies)
Ambient temperature under bias
Storage temperature
Junction temperature
Lead temperature (soldering)
Package temperature (IR reflow, peak)
(1)
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2)
PCM1850 (PCM1851)
ELECTRICAL CHARACTERISTICS
All specifications at T
A
= 25°C, V
CC
= 5 V, V
DD
= 3.3 V, master mode, f
S
= 48 kHz, system clock = 256 f
S
, 24-bit data, unless otherwise noted
PARAMETER
DIGITAL INPUT/OUTPUT
DATA FORMAT
Audio data interface format
Audio data bit length
Audio data format
f
S
Sampling frequency
256 f
S
System clock frequency
384 f
S
512 f
S
768 f
S
INPUT LOGIC
V
IH (1)
V
IL (1)
V
IH (2) (3)
V
IL (2) (3)
I
IH (2)
I
IL (2)
I
IH (1) (3)
I
IL (1) (3)
(1)
(2)
TEST CONDITIONS
PCM1850PJT PCM1851PJT
,
MIN
TYP
MAX
UNIT
Left-justified, I
2
S, right-justified
16, 24
MSB-first, 2s complement
16
4.096
6.144
8.192
12.288
2
48
12.288
18.432
24.576
36.864
96
24.576
36.864
49.152
—
V
DD
0.8
5.5
0.8
±10
±10
65
100
±10
µA
A
VDC
MHz
kHz
bits
Input logic level
0
2
0
V
IN
= V
DD
V
IN
= 0
V
IN
= V
DD
V
IN
= 0
Input logic current
Pins 1, 2: LRCK, BCK (In slave mode, Schmitt-trigger input, with 50-kΩ typical pulldown resistor)
Pins 7, 31, 32: SCKI, MC/SCL (PCM1850/1851), MD/SDA (PCM1850/1851) (Schmitt-trigger input, 5-V tolerant)
(3)
Pins 8–10, 30: TEST0, TEST1, RST, MS/ADR (PCM1850/1851) (Schmitt-trigger input, with 50-kΩ typical pulldown resistor, 5-V tolerant)
5
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