Am45DL32x8G
Data Sheet
July 2003
The following document specifies Spansion memory products that are now offered by both Advanced
Micro Devices and Fujitsu. Although the document is marked with the name of the company that orig-
inally developed the specification, these products will be offered to customers of both AMD and
Fujitsu.
Continuity of Specifications
There is no change to this datasheet as a result of offering the device as a Spansion product. Any
changes that have been made are the result of normal datasheet improvement and are noted in the
document revision summary, where supported. Future routine revisions will occur when appropriate,
and changes will be noted in a revision summary.
Continuity of Ordering Part Numbers
AMD and Fujitsu continue to support existing part numbers beginning with “Am” and “MBM”. To order
these products, please use only the Ordering Part Numbers listed in this document.
For More Information
Please contact your local AMD or Fujitsu sales office for additional information about Spansion
memory solutions.
Publication Number
26502
Revision
A
Amendment
+3
Issue Date
August 28, 2002
PRELIMINARY
Am45DL32x8G
Stacked Multi-Chip Package (MCP) Flash Memory and SRAM
32 Megabit (4 M x 8-Bit/2 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Read/Write Flash
Memory and 8 Mbit (1 M x 8-Bit/512 K x 16-Bit) CompactCell
TM
Static RAM
DISTINCTIVE CHARACTERISTICS
MCP Features
s
Power supply voltage of 2.7 to 3.3 volt
s
High performance
— Access time as fast as 70 ns
SOFTWARE FEATURES
s
Data Management Software (DMS)
— AMD-supplied software manages data programming,
enabling EEPROM emulation
— Eases historical sector erase flash limitations
s
Package
— 73-Ball FBGA
s
Supports Common Flash Memory Interface (CFI)
s
Program/Erase Suspend/Erase Resume
— Suspends program/erase operations to allow
programming/erasing in same bank
s
Operating Temperature
— –40°C to +85°C
Flash Memory Features
ARCHITECTURAL ADVANTAGES
s
Simultaneous Read/Write operations
— Data can be continuously read from one bank while
executing erase/program functions in the other bank.
— Zero latency between read and write operations
s
Data# Polling and Toggle Bits
— Provides a software method of detecting the status of
program or erase cycles
s
Unlock Bypass Program command
— Reduces overall programming time when issuing multiple
program command sequences
HARDWARE FEATURES
s
Any combination of sectors can be erased
s
Ready/Busy# output (RY/BY#)
— Hardware method for detecting program or erase cycle
completion
s
Manufactured on 0.17 µm process technology
s
SecSi™ (Secured Silicon) Sector: Extra 256 Byte sector
—
Factory locked and identifiable:
16 bytes available for
secure, random factory Electronic Serial Number; verifiable
as factory locked through autoselect function. ExpressFlash
option allows entire sector to be available for
factory-secured data
—
Customer lockable:
Sector is one-time programmable. Once
sector is locked, data cannot be changed.
s
Hardware reset pin (RESET#)
— Hardware method of resetting the internal state machine to
the read mode
s
WP#/ACC input pin
— Write protect (WP#) function protects sectors 0 and 1, or 69
and 70, regardless of sector protect status
— Acceleration (ACC) function accelerates program timing
s
Zero Power Operation
— Sophisticated power management circuits reduce power
consumed during inactive periods to nearly zero.
s
Top or bottom boot sectors
s
Compatible with JEDEC standards
— Pinout and software compatible with single-power-supply
flash standard
s
Sector protection
— Hardware method of locking a sector, either in-system or
using programming equipment, to prevent any program or
erase operation within that sector
— Temporary Sector Unprotect allows changing data in
protected sectors in-system
PERFORMANCE CHARACTERISTICS
s
High performance
— Access time as fast as 70 ns
— Program time: 4 µs/word typical utilizing Accelerate function
CompactCell SRAM Features
s
Power dissipation
— Operating: 30 mA maximum
— Standby: 100 µA maximum
s
Ultra low power consumption (typical values)
— 2 mA active read current at 1 MHz
— 10 mA active read current at 5 MHz
— 200 nA in standby or automatic sleep mode
s
CE1s# and CE2s Chip Select
s
Power down features using CE1s# and CE2s
s
Data retention supply voltage: 2.7 to 3.3 volt
s
Byte data control: LB#s (DQ7–DQ0), UB#s (DQ15–DQ8)
s
Minimum 1 million erase cycles guaranteed per sector
s
20 year data retention at 125°C
— Reliable operation for the life of the system
This document contains information on a product under development at Advanced Micro Devices. The information
is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed
product without notice.
Publication#
26502
Rev:
A
Amendment/+3
Issue Date:
August 28, 2002
Refer to AMD’s Website (www.amd.com) for the latest information.
P R E L I M I N A R Y
GENERAL DESCRIPTION
Am29DL32xG Features
The Am29DL322G/323G/324G consists of 32 megabit,
3.0 volt-only flash memory devices, organized as
2,097,152 words of 16 bits each or 4,194,304 bytes of
8 bits each. Word mode data appears on DQ15–DQ0;
byte mode data appears on DQ7–DQ0. The device is
designed to be programmed in-system with the stan-
dard 3.0 volt V
CC
supply, and can also be programmed
in standard EPROM programmers.
The devices are available with access times of 70 and
85 ns. The device is offered in a 73-ball FBGA pack-
age. Standard control pins—chip enable (CE#f), write
enable (WE#), and output enable (OE#)—control nor-
mal read and write operations, and avoid bus
contention issues.
The devices requires only a
single 3.0 volt power
supply
for both read and write functions. Internally
generated and regulated voltages are provided for the
program and erase operations.
DMS (Data Management Software)
allows systems
to easily take advantage of the advanced architecture
of the simultaneous read/write product line by allowing
removal of EEPROM devices. DMS will also allow the
system software to be simplified, as it will perform all
functions necessary to modify data in file structures,
as opposed to single-byte modifications. To write or
update a particular piece of data (a phone number or
configuration data, for example), the user only needs
to state which piece of data is to be updated, and
where the updated data is located in the system. This
is a n a d va n t a g e co m p a r e d t o sys t e ms w h e r e
user-written software must keep track of the old data
location, status, logical to physical translation of the
data onto the Flash memory device (or memory de-
vices), and more. Using DMS, user-written software
does not need to interface with the Flash memory di-
rectly. Instead, the user's software accesses the Flash
memory by calling one of only six functions. AMD pro-
vides this software to simplify system design and
software integration efforts.
The device offers complete compatibility with the
JEDEC single-power-supply Flash command set
standard.
Commands are written to the command
register using standard microprocessor write timings.
Reading data out of the device is similar to reading
from other Flash or EPROM devices.
The host system can detect whether a program or
erase operation is complete by using the device
sta-
tus bits:
RY/BY# pin, DQ7 (Data# Polling) and
DQ6/DQ2 (toggle bits). After a program or erase cycle
has been completed, the device automatically returns
to reading array data.
The
sector erase architecture
allows memory sec-
tors to be erased and reprogrammed without affecting
the data contents of other sectors. The device is fully
erased when shipped from the factory.
Hardware data protection
measures include a low
V
CC
detector that automatically inhibits write opera-
tions during power transitions. The
hardware sector
protection
feature disables both program and erase
operations in any combination of the sectors of mem-
o r y. T h i s c a n b e a c h i e v e d i n - s y s t e m o r v i a
programming equipment.
The device offers two power-saving features. When
addresses have been stable for a specified amount of
time, the device enters the
automatic sleep mode.
The system can also place the device into the
standby mode.
Power consumption is greatly re-
duced in both modes.
Simultaneous Read/Write Operations with
Zero Latency
The Simultaneous Read/Write architecture provides
simultaneous operation
by dividing the memory
space into two banks. The device can improve overall
system performance by allowing a host system to pro-
gram or erase in one bank, then immediately and
simultaneously read from the other bank, with zero la-
tency. This releases the system from waiting for the
completion of program or erase operations.
The Am29DL32xG device family uses multiple bank
architectures to provide flexibility for different applica-
tions. Three devices are available with the following
bank sizes:
Device
DL322
DL323
DL324
Bank 1
4
8
16
Bank 2
28
24
16
The
Secured Silicon (SecSi) Sector
is an extra 256
byte sector capable of being permanently locked by
AMD or customers. The
SecSi Sector Indicator Bit
(DQ7) is permanently set to a 1 if the part is
factory
locked,
and set to a 0 if
customer lockable.
This
way, customer lockable parts can never be used to re-
place a factory locked part.
Factory locked parts provide several options. The
SecSi Sector may store a secure, random 16 byte
ESN (Electronic Serial Number). Customer lockable
devices are one-time programmable and one-time
lockable.
2
Am45DL32x8G
August 28, 2002
P R E L I M I N A R Y
TABLE OF CONTENTS
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 5
MCP Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . 5
Flash memory Block Diagram . . . . . . . . . . . . . . . 6
Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . 7
Special Package Handling Instructions .................................... 7
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 9
MCP Device Bus Operations . . . . . . . . . . . . . . . . . 9
Table 2. Device Bus Operations—Flash Word Mode, CIOf = V
IH
; CC
SRAM Byte Mode, CIOs = V
SS
......................................................11
Table 3. Device Bus Operations—Flash Byte Mode, CIOf = V
SS
; CC
SRAM Word Mode, CIOs = V
CC
.....................................................12
Table 4. Device Bus Operations—Flash Byte Mode, CIOf = V
IL
; CC
SRAM Byte Mode, CIOs = V
SS
......................................................13
Figure 5. Data# Polling Algorithm .................................................. 33
DQ6: Toggle Bit I .................................................................... 34
Figure 6. Toggle Bit Algorithm........................................................ 34
DQ2: Toggle Bit II ................................................................... 35
Reading Toggle Bits DQ6/DQ2 ............................................... 35
DQ5: Exceeded Timing Limits ................................................ 35
DQ3: Sector Erase Timer ....................................................... 35
Table 20. Write Operation Status ................................................... 36
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 37
Figure 7. Maximum Negative Overshoot Waveform ...................... 37
Figure 8. Maximum Positive Overshoot Waveform........................ 37
Flash DC Characteristics . . . . . . . . . . . . . . . . . . 38
CMOS Compatible .................................................................. 38
Figure 9. I
CC1
Current vs. Time (Showing Active and
Automatic Sleep Currents) ............................................................. 39
Figure 10. Typical I
CC1
vs. Frequency............................................ 39
Flash Device Bus Operations . . . . . . . . . . . . . . . 13
Requirements for Reading Array Data ................................... 13
Writing Commands/Command Sequences ............................ 14
Accelerated Program Operation .......................................... 14
Autoselect Functions ........................................................... 14
Simultaneous Read/Write Operations with Zero Latency ....... 14
Automatic Sleep Mode ........................................................... 15
RESET#: Hardware Reset Pin ............................................... 15
Output Disable Mode .............................................................. 15
Table 5. Device Bank Division ........................................................15
Table 6. Top Boot Sector Addresses .............................................16
Table 8. Bottom Boot Sector Addresses .........................................18
Table 10. Top Boot Sector/Sector Block Addresses
for Protection/Unprotection .............................................................20
Table 11. Bottom Boot Sector/Sector Block Addresses
for Protection/Unprotection .............................................................20
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 11. Test Setup.................................................................... 41
Figure 12. Input Waveforms and Measurement Levels ................. 41
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 42
CompactCell SRAM CE#s Timing .......................................... 42
Figure 13. Timing Diagram for Alternating
Between CompactCell SRAM and Flash ....................................... 42
Read-Only Operations ........................................................... 43
Figure 14. Read Operation Timings............................................... 43
Hardware Reset (RESET#) .................................................... 44
Figure 15. Reset Timings ............................................................... 44
Word/Byte Configuration (CIOf) .............................................. 45
Figure 16. CIOf Timings for Read Operations................................ 45
Figure 17. CIOf Timings for Write Operations................................ 45
Write Protect (WP#) ................................................................ 21
Temporary Sector Unprotect .................................................. 21
Figure 1. Temporary Sector Unprotect Operation........................... 21
Figure 2. In-System Sector Protect/Unprotect Algorithms .............. 22
Flash Erase and Program Operations .................................... 46
Figure 18. Program Operation Timings..........................................
Figure 19. Accelerated Program Timing Diagram..........................
Figure 20. Chip/Sector Erase Operation Timings ..........................
Figure 21. Back-to-back Read/Write Cycle Timings ......................
Figure 22. Data# Polling Timings (During Embedded Algorithms).
Figure 23. Toggle Bit Timings (During Embedded Algorithms)......
Figure 24. DQ2 vs. DQ6.................................................................
47
47
48
49
49
50
50
SecSi™ (Secured Silicon) Sector
Flash Memory Region ............................................................ 23
Hardware Data Protection ...................................................... 23
Low V
CC
Write Inhibit ........................................................... 24
Write Pulse “Glitch” Protection ............................................ 24
Logical Inhibit ...................................................................... 24
Power-Up Write Inhibit ......................................................... 24
Common Flash Memory Interface (CFI) . . . . . . . 24
Flash Command Definitions . . . . . . . . . . . . . . . . 27
Reading Array Data ................................................................ 27
Reset Command ..................................................................... 27
Autoselect Command Sequence ............................................ 27
Enter SecSi™ Sector/Exit SecSi Sector
Command Sequence .............................................................. 27
Byte/Word Program Command Sequence ............................. 28
Unlock Bypass Command Sequence .................................. 28
Figure 3. Program Operation .......................................................... 29
Temporary Sector Unprotect .................................................. 51
Figure 25. Temporary Sector Unprotect Timing Diagram .............. 51
Figure 26. Sector/Sector Block Protect and
Unprotect Timing Diagram ............................................................. 52
Alternate CE#f Controlled Erase and Program Operations .... 53
Figure 27. Flash Alternate CE#f Controlled Write (Erase/Program)
Operation Timings.......................................................................... 54
Power Up Time ....................................................................... 55
Read Cycle ............................................................................. 55
Figure 28. CompactCell SRAM Read Cycle—Address Controlled 55
Read Cycle ............................................................................. 56
Figure 29. CompactCell SRAM Read Cycle .................................. 56
Write Cycle ............................................................................. 57
Figure 30. CompactCell SRAM Write Cycle—WE# Control........... 57
Figure 31. CompactCell SRAM Write Cycle—CE1#s Control........ 58
Figure 32. CompactCell SRAM Write Cycle—
UB#s and LB#s Control.................................................................. 59
Chip Erase Command Sequence ........................................... 29
Sector Erase Command Sequence ........................................ 29
Erase Suspend/Erase Resume Commands ........................... 30
Figure 4. Erase Operation............................................................... 30
Table 17. Autoselect Device IDs (Word Mode) ...............................31
Table 19. Autoselect Device IDs (Byte Mode) ................................32
Flash Write Operation Status . . . . . . . . . . . . . . . . 33
DQ7: Data# Polling ................................................................. 33
Flash Erase And Programming Performance . .
Latchup Characteristics . . . . . . . . . . . . . . . . . . . .
Package Pin Capacitance. . . . . . . . . . . . . . . . . . .
Flash Data Retention . . . . . . . . . . . . . . . . . . . . . .
60
60
60
60
August 28, 2002
Am45DL32x8G
3
P R E L I M I N A R Y
SRAM Data Retention . . . . . . . . . . . . . . . . . . . . . . 61
Figure 33. CE1#s Controlled Data Retention Mode........................ 61
Figure 34. CE2s Controlled Data Retention Mode.......................... 61
FLB073—73-Ball Fine-Pitch Grid Array 8 x 11.6 mm ............. 62
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 63
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 62
4
Am45DL32x8G
August 28, 2002
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