MT55L128V32F1T-10 datasheet, PDF

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MT55L128V32F1T-10: DescriptionZBT SRAM, 128KX32, 7.5ns, CMOS, PQFP100, PLASTIC, MS-026, TQFP-100; Categorystorage storage; File Size366KB，26 Pages; ManufacturerMicron Technology; Websitehttp://www.mdtic.com.tw/

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MT55L128V32F1T-10 Overview

ZBT SRAM, 128KX32, 7.5ns, CMOS, PQFP100, PLASTIC, MS-026, TQFP-100

MT55L128V32F1T-10 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Micron Technology
Parts packaging code	QFP
package instruction	PLASTIC, MS-026, TQFP-100
Contacts	100
Reach Compliance Code	not_compliant
ECCN code	3A991.B.2.A
Maximum access time	7.5 ns
Other features	FLOW-THROUGH ARCHITECTURE
Maximum clock frequency (fCLK)	100 MHz
I/O type	COMMON
JESD-30 code	R-PQFP-G100
JESD-609 code	e0
length	20 mm
memory density	4194304 bit
Memory IC Type	ZBT SRAM
memory width	32
Number of functions	1
Number of terminals	100
word count	131072 words
character code	128000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	128KX32
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	LQFP
Encapsulate equivalent code	QFP100,.63X.87
Package shape	RECTANGULAR
Package form	FLATPACK, LOW PROFILE
Parallel/Serial	PARALLEL
power supply	2.5,3.3 V
Certification status	Not Qualified
Maximum seat height	1.6 mm
Maximum standby current	0.01 A
Minimum standby current	3.14 V
Maximum slew rate	0.3 mA
Maximum supply voltage (Vsup)	3.465 V
Minimum supply voltage (Vsup)	3.135 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	GULL WING
Terminal pitch	0.65 mm
Terminal location	QUAD
width	14 mm

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4Mb: 256K x 18, 128K x 32/36

FLOW-THROUGH ZBT SRAM

4Mb

ZBT

SRAM

FEATURES

•

High frequency and 100 percent bus utilization

Fast cycle times: 10ns, 11ns, and 12ns

Single +3.3V ±5% power supply (V

)

Separate +3.3V or +2.5V isolated output buffer

supply (V

Advanced control logic for minimum control

signal interface

Individual BYTE WRITE controls may be tied LOW

Single R/W# (read/write) control pin

CKE# pin to enable clock and suspend operations

Three chip enables for simple depth expansion

Clock-controlled and registered addresses, data

I/Os and control signals

Internally self-timed, fully coherent WRITE

Internally self-timed, registered outputs to

eliminate the need to control OE#

SNOOZE MODE for reduced-power standby

Common data inputs and data outputs

Linear or interleaved burst modes

Burst feature (optional)

Pin/function compatibility with 2Mb, 8Mb, and

16Mb ZBT SRAM family

165-pin FBGA package

100-pin TSOP package

Automatic power-down

MT55L256L18F1, MT55L128L32F1,

MT55L128L36F1; MT55L256V18F1,

MT55L128V32F1, MT55L128V36F1

3.3V V

, 3.3V or 2.5V I/O

100-Pin TQFP

165-Pin FBGA

OPTIONS

• Timing (Access/Cycle/MHz)

7.5ns/10ns/100 MHz

8.5ns/11ns/90 MHz

9ns/12ns/83 MHz

• Configurations

3.3V I/O

256K x 18

128K x 32

128K x 36

2.5V I/O

256K x 18

128K x 32

128K x 36

• Package

100-pin TQFP

165-pin FBGA

• Operating Temperature Range

Commercial (0°C to +70°C)

Industrial (-40°C to +85°C)**

Part Number Example:

MARKING

-10

-11

-12

NOTE:

1. JEDEC-standard MS-026 BHA (LQFP).

MT55L256L18F1

MT55L128L32F1

MT55L128L36F1

MT55L256V18F1

MT55L128V32F1

MT55L128V36F1

None

* A Part Marking Guide for the FBGA devices can be found on Micron’s

Web site—http://www.micron.com/support/index.html.

** Industrial temperature range offered in specific speed grades and

configurations. Contact factory for more information.

GENERAL DESCRIPTION

The Micron

Zero Bus Turnaround

™

(ZBT

) SRAM

family employs high-speed, low-power CMOS designs

using an advanced CMOS process.

Micron’s 4Mb ZBT SRAMs integrate a 256K x 18,

128K x 32, or 128K x 36 SRAM core with advanced

synchronous peripheral circuitry and a 2-bit burst

counter. These SRAMs are optimized for 100 percent

bus utilization, eliminating any turnaround cycles when

transitioning from READ to WRITE, or vice versa. All

synchronous inputs pass through registers controlled

by a positive-edge-triggered single clock input (CLK).

MT55L256L18F1T-12

4Mb: 256K x 18, 128K x 32/36 Flow-Through ZBT SRAM

MT55L256L18F1_E.p65 – Rev. 2/02

Micron Technology, Inc., reserves the right to change products or specifications without notice.

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