IS62LV256L
32K x 8 LOW VOLTAGE
CMOS STATIC RAM
FEATURES
• High-speed access time: 15, 20, 25 ns
• Automatic power-down when chip is deselected
• CMOS low power operation
— 255 mW (max.) operating
— 0.18 mW (max.) CMOS standby
• TTL compatible interface levels
• Single 3.3V power supply
• Fully static operation: no clock or refresh
required
• Three-state outputs
DESCRIPTION
The
ICSI
IS62LV256L is a very high-speed, low power,
32,768-word by 8-bit static RAM. It is fabricated using
ICSI
's
high-performance CMOS technology. This highly reliable pro-
cess coupled with innovative circuit design techniques, yields
access times as fast as 15 ns maximum.
When
CE
is HIGH (deselected), the device assumes a standby
mode at which the power dissipation is reduced to
50 µW (typical) with CMOS input levels.
Easy memory expansion is provided by using an active LOW
Chip Enable (CE). The active LOW Write Enable (WE) controls
both writing and reading of the memory.
The IS62LV256L is available in the JEDEC standard 28-pin
300mil SOJ and the 8*13.4mm TSOP-1 package.
FUNCTIONAL BLOCK DIAGRAM
A0-A14
DECODER
256 X 1024
MEMORY ARRAY
VCC
GND
I/O
DATA
CIRCUIT
I/O0-I/O7
COLUMN I/O
CE
OE
WE
CONTROL
CIRCUIT
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.
Integrated Circuit Solution Inc.
SR007-0B
1
IS62LV256L
PIN CONFIGURATION
28-Pin SOJ
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
WE
A13
A8
A9
A11
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
PIN CONFIGURATION
8x13.4mm TSOP-1
OE
A11
A9
A8
A13
WE
VCC
A14
A12
A7
A6
A5
A4
A3
22
23
24
25
26
27
28
1
2
3
4
5
6
7
21
20
19
18
17
16
15
14
13
12
11
10
9
8
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A1
A2
PIN DESCRIPTIONS
A0-A14
CE
OE
WE
I/O0-I/O7
Vcc
GND
Address Inputs
Chip Enable Input
Output Enable Input
Write Enable Input
Input/Output
Power
Ground
TRUTH TABLE
Mode
Not Selected
(Power-down)
Output Disabled
Read
Write
WE
X
H
H
L
CE
H
L
L
L
OE
X
H
L
X
I/O Operation
High-Z
High-Z
D
OUT
D
IN
Vcc Current
I
SB
1
, I
SB
2
I
CC
1
, I
CC
2
I
CC
1
, I
CC
2
I
CC
1
, I
CC
2
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
TERM
T
BIAS
T
STG
P
T
I
OUT
Parameter
Terminal Voltage with Respect to GND
Temperature Under Bias
Storage Temperature
Power Dissipation
DC Output Current (LOW)
Value
–0.5 to +4.6
–55 to +125
–65 to +150
0.5
20
Unit
V
°C
°C
W
mA
Note:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
2
Integrated Circuit Solution Inc.
SR007-0B
IS62LV256L
OPERATING RANGE
Range
Commercial
Industrial
Ambient Temperature
0°C to +70°C
–40°C to +85°C
V
CC
3.3V +10%
3.3V ± 10%
DC ELECTRICAL CHARACTERISTICS
(Over Operating Range)
Symbol
V
OH
V
OL
V
IH
V
IL
I
LI
I
LO
Parameter
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
(1)
Input Leakage
Output Leakage
GND
≤
V
IN
≤
V
CC
GND
≤
V
OUT
≤
V
CC
, Outputs Disabled
Com.
Ind.
Com.
Ind.
Test Conditions
V
CC
= Min., I
OH
= –2.0 mA
V
CC
= Min., I
OL
= 4.0 mA
Min.
2.4
—
2.2
–0.3
–2
–5
–2
–5
Max.
—
0.4
V
CC
+ 0.3
0.8
2
5
2
5
Unit
V
V
V
V
µA
µA
Notes:
1. V
IL
= –3.0V for pulse width less than 10 ns.
2. Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.
POWER SUPPLY CHARACTERISTICS
(1)
(Over Operating Range)
Symbol Parameter
I
CC
1
I
CC
2
I
SB
1
Vcc Operating
Supply Current
Vcc Dynamic Operating
Supply Current
TTL Standby Current
(TTL Inputs)
CMOS Standby
Current (CMOS Inputs)
Test Conditions
V
CC
= Max.,
CE
= V
IL
I
OUT
= 0 mA, f = 0
V
CC
= Max.,
CE
= V
IL
I
OUT
= 0 mA, f = f
MAX
V
CC
= Max.,
V
IN
= V
IH
or V
IL
CE
≥
V
IH
, f = 0
V
CC
= Max.,
CE
≤
V
CC
– 0.2V,
V
IN
> V
CC
– 0.2V, or
V
IN
≤
0.2V, f = 0
Com.
Ind.
Com.
Ind.
Com.
Ind.
Com.
Ind.
-15 ns
Min. Max.
—
—
—
—
—
—
—
—
50
60
70
70
3
5
50
100
-20 ns
Min. Max.
—
—
—
—
—
—
—
—
50
60
60
60
3
5
50
100
-25 ns
Min. Max.
—
—
—
—
—
—
50
60
50
50
3
5
Unit
mA
mA
mA
I
SB
2
— 50
— 100
µA
Note:
1. At f = f
MAX
, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
CAPACITANCE
(1,2)
Symbol
C
IN
C
OUT
Parameter
Input Capacitance
Output Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
Max.
6
5
Unit
pF
pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: T
A
= 25°C, f = 1 MHz, Vcc = 3.3V.
Integrated Circuit Solution Inc.
SR007-0B
3
IS62LV256L
READ CYCLE SWITCHING CHARACTERISTICS
(1)
(Over Operating Range)
Symbol
Parameter
Read Cycle Time
Address Access Time
Output Hold Time
CE
Access Time
OE
Access Time
OE
to Low-Z Output
OE
to High-Z Output
CE
to Low-Z Output
CE
to High-Z Output
CE
to Power-Up
CE
to Power-Down
-15 ns
Min. Max.
15
—
2
—
—
0
—
3
—
0
—
—
15
—
15
7
—
8
—
6
—
15
-20 ns
Min. Max.
20
—
2
—
—
0
—
3
—
0
—
—
20
—
20
8
—
9
—
9
—
18
-25 ns
Min. Max.
25
—
2
—
—
0
—
3
—
0
—
—
25
—
25
9
—
10
—
10
—
20
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
(2)
t
HZOE
(2)
t
LZCE
(2)
t
HZCE
(2)
t
PU
(3)
t
PD
(3)
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V
and output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. Not 100% tested.
AC TEST CONDITIONS
Parameter
Input Pulse Level
Input Rise and Fall Times
Input and Output Timing
and Reference Levels
Output Load
Unit
0V to 3.0V
3 ns
1.5V
See Figures 1 and 2
AC TEST LOADS
635
Ω
3.3V
3.3V
635
Ω
OUTPUT
30 pF
Including
jig and
scope
702
Ω
OUTPUT
5 pF
Including
jig and
scope
702
Ω
Figure 1.
Figure 2.
4
Integrated Circuit Solution Inc.
SR007-0B
IS62LV256L
AC WAVEFORMS
READ CYCLE NO. 1
(1,2)
t
RC
ADDRESS
t
AA
t
OHA
t
OHA
DATA VALID
D
OUT
READ CYCLE NO. 2
(1,3)
t
RC
ADDRESS
t
AA
t
OHA
OE
t
DOE
t
HZOE
CE
t
ACE
t
LZCE
t
LZOE
t
HZCE
DATA VALID
D
OUT
HIGH-Z
t
PU
t
PD
50%
50%
ICC
SUPPLY
CURRENT
ISB
Notes:
1.
WE
is HIGH for a Read Cycle.
2. The device is continuously selected.
OE, CE
= V
IL
.
3. Address is valid prior to or coincident with
CE
LOW transitions.
Integrated Circuit Solution Inc.
SR007-0B
5
京公网安备 11010802033920号
EEWORLD
