Preliminary
GS4288S09/18L
144-Ball
BGA
Commercial Temp
Industrial Temp
Features
• Pin- and function-compatible with Micron RLDRAM® II
• 533 MHz DDR operation (1.067Gb/s/pin data rate)
• 38.4 Gb/s peak bandwidth (x18 at 533 MHz clock frequency)
• 16M x 18 and 32M x 9 organizations available
• 8 banks
• Reduced cycle time (15 ns at 533 MHz)
• Address Multiplexing (Nonmultiplexed address option
available)
• SRAM-type interface
• Programmable Read Latency (RL), row cycle time, and burst
sequence length
• Balanced Read and Write Latencies in order to optimize data
bus utilization
• Data mask for Write commands
• Differential input clocks (CK, CK)
• Differential input data clocks (DKx, DKx)
• On-chip DLL generates CK edge-aligned data and output
data clock signals
• Data valid signal (QVLD)
• 32 ms refresh (8K refresh for each bank; 64K refresh
command must be issued in total each 32 ms)
• 144-ball
BGA
package
• HSTL I/O (1.5 V or 1.8 V nominal)
• 25–60 matched impedance outputs
• 2.5 V V
EXT
, 1.8 V V
DD
, 1.5 V or 1.8 V V
DDQ
I/O
• On-die termination (ODT) R
TT
• Commerical and Industrial Temperature
Commercial (+0°
T
C
+95°C)
Industrial (–40°
T
C
+95°C)
32M x 9, 16M x 18
288Mb SIO Low Latency DRAM (LLDRAM) II
Introduction
533 MHz–300 MHz
2.5 V V
EXT
1.8 V V
DD
1.5 V or 1.8 V V
DDQ
The GSI Technology 288Mb Low Latency DRAM
(LLDRAM) II is a high speed memory device designed for
high address rate data processing typically found in networking
and telecommunications applications. The 8-bank architecture
and low tRC allows access rates formerly only found in
SRAMs.
The Double Data Rate (DDR) I/O interface provides high
bandwidth data transfers, clocking out two beats of data per
clock cycle at the I/O balls. Source-synchronous clocking can
be implemented on the host device with the provided free-
running data output clock.
Commands, addresses, and control signals are single data rate
signals clocked in by the True differential input clock
transition, while input data is clocked in on both crossings of
the input data clock(s).
Read and Write data transfers always in short bursts. The burst
length is programmable to 2, 4 or 8 by setting the Mode
Register.
The device is supplied with 2.5 V V
EXT
and 1.8 V V
DD
for the
core, and 1.5 V or 1.8 V for the HSTL output drivers.
Internally generated row addresses facilitate bank-scheduled
refresh.
The device is delivered in an efficent
BGA
144-ball package.
Rev: 1.02 3/2013
1/63
© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS4288S09/18L
32M x 9 Mb Ball Assignments—144-Ball
BGA—Top
View
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
V
REF
V
DD
V
TT
A22
1
A21
1
A5
A8
BA2
NF
2
DK
REF
WE
A18
A15
V
SS
V
TT
V
DD
V
REF
2
V
SS
DNU
3
DNU
3
DNU
3
DNU
3
DNU
3
A6
A9
NF
2
DK
CS
A16
DNU
3
DNU
3
DNU
3
DNU
3
DNU
3
ZQ
3
V
EXT
DNU
3
DNU
3
DNU
3
DNU
3
DNU
3
A7
V
SS
V
DD
V
DD
V
SS
A17
DNU
3
DNU
3
DNU
3
DNU
3
DNU
3
V
EXT
4
V
SS
V
SS
V
DDQ
V
SS
V
DDQ
V
SS
V
DD
V
SS
V
DD
V
DD
V
SS
V
DD
V
SS
V
DDQ
V
SS
V
DDQ
V
SS
V
SS
5
6
7
8
9
V
SS
V
SS
V
DDQ
V
SS
V
DDQ
V
SS
V
DD
V
SS
V
DD
V
DD
V
SS
V
DD
V
SS
V
DDQ
V
SS
V
DDQ
V
SS
V
SS
10
V
EXT
Q0
Q1
QK0
Q2
Q3
A2
V
SS
V
DD
V
DD
V
SS
A12
Q4
Q5
Q6
Q7
Q8
V
EXT
11
TMS
D0
D1
QK0
D2
D3
A1
A4
BA0
BA1
A14
A11
D4
D5
D6
D7
D8
TDO
12
TCK
V
DD
V
TT
V
SS
A20
QVLD
A0
A3
CK
CK
A13
A10
A19
DM
V
SS
V
TT
V
DD
TDI
Notes:
1. Reserved for future use. This pin may be connected to ground.
2. No function. This pin may have parasitic characteristics of a clock input signal. It may be connected to GND.
3. Do not use. This pin may have parasitic characteristics of an I/O. It may be connected to GND.
Rev: 1.02 3/2013
2/63
© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS4288S09/18L
16M x 18 Ball Assignments—144-Ball
BGA—Top
View
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
V
REF
V
DD
V
TT
A22
1
A21
1
A5
A8
BA2
NF
3
DK
REF
WE
A18
A15
V
SS
V
TT
V
DD
V
REF
2
V
SS
D4
D5
D6
D7
D8
A6
A9
NF
3
DK
CS
A16
D14
D15
QK1
D16
D17
ZQ
3
V
EXT
Q4
Q5
Q6
Q7
Q8
A7
V
SS
V
DD
V
DD
V
SS
A17
Q14
Q15
QK1
Q16
Q17
V
EXT
4
V
SS
V
SS
V
DDQ
V
SS
V
DDQ
V
SS
V
DD
V
SS
V
DD
V
DD
V
SS
V
DD
V
SS
V
DDQ
V
SS
V
DDQ
V
SS
V
SS
5
6
7
8
9
V
SS
V
SS
V
DDQ
V
SS
V
DDQ
V
SS
V
DD
V
SS
V
DD
V
DD
V
SS
V
DD
V
SS
V
DDQ
V
SS
V
DDQ
V
SS
V
SS
10
V
EXT
Q0
Q1
QK0
Q2
Q3
A2
V
SS
V
DD
V
DD
V
SS
A12
Q9
Q10
Q11
Q12
Q13
V
EXT
11
TMS
D0
D1
QK0
D2
D3
A1
A4
BA0
BA1
A14
A11
D9
D10
D11
D12
D13
TDO
12
TCK
V
DD
V
TT
V
SS
A20
2
QVLD
A0
A3
CK
CK
A13
A10
A19
DM
V
SS
V
TT
V
DD
TDI
Notes:
1. Reserved for future use. This pin may be connected to GND.
2. Reserved for future use. This pin may have parasitic characteristics of an address input signal. It may be connected to GND.
3. No function. This pin may have parasitic characteristics of a clock input signal. It may be connected to GND.
Rev: 1.02 3/2013
3/63
© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS4288S09/18L
Ball Descriptions
Symbol
A0–A20
BA0–B2
CK, CK
Type
Input
Input
Input
Input
Input
Description
Address Inputs—A0–A20
define the row and column addresses for Read and Write Operations. During
a Mode Register Set (MRS), the address inputs define the register settings. They are sampled at the
rising edge of CK.
Bank Address inputs—Select
to which internal bank a command is being applied.
Input Clock—CK
and CK are differential input clocks. Addresses and commands are latched on the
rising edge of CK. CK is ideally 180º out of phase with CK.
Chip Select—CS
enables the command decoder when Low and disables it when High. When the
command decoder is disabled, new commands are ignored, but internal operations continue.
Data Input—The
D signals form the 18-bit input data bus. During Write commands, the data is sampled
at both edges of DK.
Input Data Clock—DK
and DK are the differential input data clocks. All input data is referenced to both
edges of DK. DK is ideally 180º out of phase with DK. In both the x9 and x18 devices, all Ds are
referenced to DK and DK.
Input Data Mask—The
DM signal is the input mask signal for Write data. Input data is masked when DM
is sampled High. DM is sampled on both edges of DK. Tie signal to ground if not used.
IEEE 1149.1 clock input—This
ball must be tied to V
SS
if the JTAG function is not used.
IEEE 1149.1 test inputs—These
balls may be left as no connects if the JTAG function is not used.
Command Inputs—Sampled
at the positive edge of CK, WE and REF define (together with CS) the
command to be executed.
Input Reference Voltage—Nominally
V
DDQ
/2. Provides a reference voltage for the input buffers.
External Impedance (25–60)—This
signal is used to tune the device outputs to the system data bus
impedance. Q output impedance is set to 0.2 * RQ, where RQ is a resistor from this signal to ground.
Connecting ZQ to GND invokes the Minimum Impedance mode. Connecting ZQ to V
DD
invokes the
maximum Impedance mode. Refer to the Mode Register Definition diagrams (Mode Register Bit 8 (M8))
to activate or deactivate this function.
Q0–Q17
Output
Data Output—The
Q signals form the 18-bit output data bus. During Read commands, the data is
referenced to both edges of QK.
Output Data Clocks—QKx
and QKx are opposite polarity, output data clocks. They are free running,
and during Reads, are edge-aligned with data output from the LLDRAM II. QKx is ideally 180º out of
phase with QKx. For the x18 device, QK0 and QK0 are aligned with Q0–Q8, while QK1 and QK1 are
aligned with Q9–Q17. For the x9 device, all Qs are aligned with QK0 and QK0.
CS
D0–D17
DK, DK
Input
DM
TCK
TMS, TDI
WE, REF
V
REF
Input
Input
Input
Input
Input
ZQ
Reference
QKx, QKx
Output
Rev: 1.02 3/2013
4/63
© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS4288S09/18L
Ball Descriptions (Continued)
Symbol
QVLD
TDO
V
DD
V
DDQ
V
EXT
V
SS
V
TT
A21, A22
DNU
NF
Type
Output
Output
Supply
Supply
Supply
Supply
—
—
—
—
Description
Data Valid—The
QVLD pin indicates valid output data. QVLD is edge-aligned with QKx and QKx.
IEEE 1149.1 Test Output—JTAG
output. This ball may be left as no connect if the JTAG function is not
used.
Power Supply—Nominally,
1.8 V. See the DC Electrical Characteristics and Operating Conditions
section for range.
DQ Power Supply—Nominally,
1.5 V or 1.8 V. Isolated on the device for improved noise immunity. See
the DC Electrical Characteristics and Operating Conditions section for range.
Power Supply—Nominally,
2.5 V. See the DC Electrical Characteristics and Operating Conditions
section for range.
Ground
Power Supply—Isolated
termination supply. Nominally, V
DDQ
/2. See the DC Electrical Characteristics
and Operating Conditions section for range.
Reserved for Future Use—This
signal is not connected and may be connected to ground.
Do Not Use—These
balls may be connected to ground.
No Function—These
balls can be connected to ground.
Rev: 1.02 3/2013
5/63
© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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