K6T2008V2A, K6T2008U2A Family
Document Title
256Kx8 bit Low Power and Low Voltage CMOS Static RAM
CMOS SRAM
Revision History
Revision No.
0.0
1.0
2.0
History
Design target
Finalize
Revised
- Add FBGA type package
Draft Data
May 26, 1998
October 8, 1998
July 21, 1999
Remark
Advance
Final
Final
The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and
products. SAMSUNG Electronics will answer to your questions. If you have any questions, please contact the SAMSUNG branch offices.
Revision 2.0
July 1999
K6T2008V2A, K6T2008U2A Family
256Kx8 bit Low Power and Low Voltage CMOS Static RAM
FEATURES
•
Process Technology: TFT
•
Organization: 256Kx8
•
Power Supply Voltage
K6T2008V2A Family: 3.0V~3.6V
K6T2008U2A Family: 2.7V~3.3V
•
Low Data Retention Voltage: 2V(Min)
•
Three state output and TTL Compatible
•
Package Type: 32-TSOP1-0820F, 32-TSOP1-0813.4F
48-FBGA-6.00x7.00
CMOS SRAM
GENERAL DESCRIPTION
The K6T2008V2A and K6T2008U2A families are fabricated by
SAMSUNG′s advanced CMOS process technology. The fam-
ily support various operating temperature ranges and have
various package types for user flexibility of system design. The
family also support low data retention voltage for battery back-
up operation with low data retention current.
PRODUCT FAMILY
Power Dissipation
Product Family
Operating Temperature Vcc Range
Speed
Standby
(I
SB1
, Max)
10µA
30mA
15µA
2)
Operating
(I
CC2,
Max)
PKG Type
K6T2008V2A-B
K6T2008U2A-B
K6T2008V2A-F
K6T2008U2A-F
Commercial(0~70°C)
3.0~3.6V
2.7~3.3V
70/85ns
70
1)
/85/100ns
70
1)
/85/100ns
Industrial(-40~85°C)
3.0~3.6V
2.7~3.3V
32-TSOP1-0820F
32-TSOP1-0813.4F
48-FBGA-6.00x7.00
1. The parameters are tested with 30pF test load
2. K6T2008V2A Family = 35mA
PIN DESCRIPTION
1
A11
A9
A8
A13
WE
CS2
A15
V
CC
A17
A16
A14
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
A10 A
CS1
I/O8
I/O7 B
I/O6
I/O5
I/O4 C
V
SS
I/O3
I/O2
D
I/O1
A0
A1
E
A2
A3
F
2
3
4
5
6
A0
A1
CS2
A3
A6
A8
FUNCTIONAL BLOCK DIAGRAM
Clk gen.
Precharge circuit.
I/O5
A2
WE
A4
A7
I/O1
A16
A15
32-TSOP1
32-sTSOP1
Type - Forward
I/O6
NC
A5
I/O2
A14
A13
Vss
Vcc
A12
A11
Row
select
Memory array
1024 rows
256×8 columns
Vcc
Vss
A10
A9
I/O7
NC
A17
I/O3
A8
A7
G
I/O8
OE
CS1
A16
A15
I/O4
H
A9
A10
A11
A12
A13
A14
I/O
1
I/O
8
Data
cont
I/O Circuit
Column select
48-FBGA: Top View (Ball Down)
Name
Function
Name
Function
Data
cont
CS
1
,CS
2
Chip Select Inputs
OE
WE
A
0
~A
17
Output Enable Input
Write Enable Input
Address Inputs
I/O
1
~I/O
8
Data Inputs/Outputs
Vcc
Vss
N.C.
Power
Ground
No Connection
CS
1
CS
2
WE
OE
A0
A1 A17 A6 A5 A4 A3
A2
Control
logic
SAMSUNG ELECTRONICS CO., LTD.
reserves the right to change products and specifications without notice.
Revision 2.0
July 1999
K6T2008V2A, K6T2008U2A Family
PRODUCT LIST
Commercial Temperature Products(0~70°C)
Part Name
K6T2008V2A-TB70
K6T2008V2A-TB85
K6T2008U2A-TB70
K6T2008U2A-TB85
K6T2008U2A-TB10
K6T2008V2A-YB70
K6T2008V2A-YB85
K6T2008U2A-YB70
K6T2008U2A-YB85
K6T2008U2A-YB10
Function
32-TSOP1 F, 70ns, 3.3V,LL
32-TSOP1 F, 85ns, 3.3V,LL
32-TSOP1 F, 70ns, 3.0V, LL
32-TSOP1 F, 85ns, 3.0V, LL
32-TSOP1 F, 100ns, 3.0V, LL
32-sTSOP1 F, 70ns, 3.3V,LL
32-sTSOP1 F, 85ns, 3.3V,LL
32-sTSOP1 F, 70ns, 3.0V, LL
32-sTSOP1 F, 85ns, 3.0V, LL
32-sTSOP1 F, 100ns, 3.0V, LL
CMOS SRAM
Industrial Temperature Products(-40~85°C)
Part Name
Function
32-TSOP1 F, 70ns, 3.3V, LL
32-TSOP1 F, 85ns, 3.3V, LL
32-TSOP1 F, 100ns, 3.3V, LL
32-TSOP1 F, 70ns, 3.0V, LL
32-TSOP1 F, 85ns, 3.0V, LL
32-TSOP1 F, 100ns, 3.0V, LL
32-sTSOP1 F, 70ns, 3.3V, LL
32-sTSOP1 F, 85ns, 3.3V, LL
32-sTSOP1 F, 100ns, 3.3V, LL
32-sTSOP1 F, 70ns, 3.0V, LL
32-sTSOP1 F, 85ns, 3.0V, LL
32-sTSOP1 F, 100ns, 3.0V, LL
48-FBGA, 70ns, 3.3V, LL
48-FBGA, 85ns, 3.3V, LL
48-FBGA, 70ns, 3.0V, LL
48-FBGA, 85ns, 3.0V, LL
K6T2008V2A-TF70
K6T2008V2A-TF85
K6T2008V2A-TF10
K6T2008U2A-TF70
K6T2008U2A-TF85
K6T2008U2A-TF10
K6T2008V2A-YF70
K6T2008V2A-YF85
K6T2008V2A-YF10
K6T2008U2A-YF70
K6T2008U2A-YF85
K6T2008U2A-YF10
K6T2008V2A-FF70
K6T2008V2A-FF85
K6T2008U2A-FF70
K6T2008U2A-FF85
FUNCTIONAL DESCRIPTION
CS
1
H
X
1)
L
L
L
CS
2
X
1)
L
H
H
H
OE
X
1)
X
1)
H
L
X
1)
WE
X
1)
X
1)
H
H
L
I/O
High-Z
High-Z
High-Z
Dout
Din
Mode
Deselected
Deselected
Output Disabled
Read
Write
Power
Standby
Standby
Active
Active
Active
1. X means don′t care (Must be in high or low states)
ABSOLUTE MAXIMUM RATINGS
1)
Item
Voltage on any pin relative to Vss
Voltage on Vcc supply relative to Vss
Power Dissipation
Storage temperature
Operating Temperature
Symbol
V
IN
,V
OUT
V
CC
P
D
T
STG
T
A
Ratings
-0.5 to V
CC
+0.5
-0.3 to 4.6
1.0
-65 to 150
0 to 70
-40 to 85
Unit
V
V
W
°C
°C
°C
Remark
-
-
-
-
K6T2008V2A-L, K6T2008U2A-L
K6T2008V2A-P, K6T2008U2A-P
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be
restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Revision 2.0
July 1999
K6T2008V2A, K6T2008U2A Family
RECOMMENDED DC OPERATING CONDITIONS
1)
Item
Supply voltage
Ground
Input high voltage
Input low voltage
Symbol
Vcc
Vss
V
IH
V
IL
Product
K6T2008V2A Family
K6T2008U2A Family
All Family
K6T2008V2A, K6T2008U2A Family
K6T2008V2A, K6T2008U2A Family
Min
3.0
2.7
0
2.2
-0.3
3)
CMOS SRAM
Typ
3.3
3.0
0
-
-
Max
3.6
3.3
0
Vcc+0.3
0.6
Unit
V
V
V
V
Note:
1. Commercial Product : T
A
=0 to 70°C, otherwise specified
Industrial Product : T
A
=-40 to 85°C, otherwise specified
2. Overshoot : Vcc+2.0V in case of pulse width≤30ns
3. Undershoot : -2.0V in case of pulse width≤30ns
4. Overshoot and undershoot are sampled, not 100% tested.
CAPACITANCE
1)
(f=1MHz, T
A
=25°C)
Item
Input capacitance
Input/Output capacitance
1. Capacitance is sampled, not 100% tested
Symbol
C
IN
C
IO
Test Condition
V
IN
=0V
V
IO
=0V
Min
-
-
Max
8
10
Unit
pF
pF
DC AND OPERATING CHARACTERISTICS
Item
Input leakage current
Output leakage current
Operating power supply current
Average operating current
Output low voltage
Output high voltage
Standby Current(TTL)
Standby Current(CMOS)
1. K6T2008V2A Family = 35mA
2. Industrial product = 15µA
Symbol
I
LI
I
LO
I
CC
I
CC1
I
CC2
V
OL
V
OH
I
SB
I
SB1
V
IN
=Vss to Vcc
Test Conditions
Min Typ Max Unit
-1
-1
-
-
-
-
2.4
-
-
-
-
-
-
25
-
-
-
0.2
1
1
5
4
30
1)
0.4
-
0.3
10
2)
µA
µA
mA
mA
mA
V
V
mA
µA
CS
1
=V
IH
or CS
2
=V
IL
or OE=V
IH
or WE=V
IL
, V
IO
=Vss to Vcc
I
IO
=0mA, CS
1
=V
IL
, CS
2
=V
IH,
V
IN
=V
IH
or V
IL
Cycle time=1µs, 100%duty, I
IO
=0mA, CS
1
≤0.2V,
CS
2
≥Vcc-0.2V,
V
IN
≤0.2V
Cycle time=Min, 100% duty, I
IO
=0mA, CS
1
=V
IL
, CS
2
=V
IH,
V
IN
=V
IH
or V
IL
I
OL
=2.1mA
I
OH
=-1.0mA
CS
1
=V
IH
, CS2=V
IL
, Other inputs=V
IH
or V
IL
CS
1
≥Vcc-0.2V,
CS
2
≥Vcc-0.2V
or CS
2
≤0.2V,
Other inputs=0~Vcc
Revision 2.0
July 1999
K6T2008V2A, K6T2008U2A Family
AC OPERATING CONDITIONS
TEST CONDITIONS
( Test Load and Input/Output Reference)
Input pulse level : 0.4 to 2.2V
Input rising and falling time : 5ns
Input and output reference voltage :1.5V
Output load(see right) : C
L
=100pF+1TTL
C
L
=30pF+1TTL
C
L
1)
CMOS SRAM
1. Including scope and jig capacitance
AC CHARACTERISTICS
(K6T2008V2A Family: V
CC
=3.0~3.6V, K6T2008U2A Family: V
CC
=2.7~3.3V
Commercial Product: T
A
=0 to 70°C, Industrial Product: T
A
=-40 to 85°C)
Speed Bins
Parameter List
Symbol
70ns
Min
Read cycle time
Address access time
Chip select to output
Output enable to valid output
Read
Chip select to low-Z output
Output enable to low-Z output
Chip disable to high-Z output
Output disable to high-Z output
Output hold from address change
Write cycle time
Chip select to end of write
Address set-up time
Address valid to end of write
Write
Write pulse width
Write recovery time
Write to output high-Z
Data to write time overlap
Data hold from write time
End write to output low-Z
t
RC
t
AA
t
CO1
, t
CO2
t
OE
t
LZ
t
OLZ
t
HZ
t
OHZ
t
OH
t
WC
t
CW
t
AS
t
AW
t
WP
t
WR
t
WHZ
t
DW
t
DH
t
OW
70
-
-
-
10
5
0
0
10
70
60
0
60
55
0
0
30
0
5
Max
-
70
70
35
-
-
25
25
-
-
-
-
-
-
-
25
-
-
-
Min
85
-
-
-
10
5
0
0
15
85
70
0
70
60
0
0
35
0
5
85ns
Max
-
85
85
40
-
-
25
25
-
-
-
-
-
-
-
30
-
-
-
100ns
Min
100
-
-
-
10
5
0
0
15
100
80
0
80
70
0
0
40
0
5
Max
-
100
100
50
-
-
30
30
-
-
-
-
-
-
-
30
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Units
DATA RETENTION CHARACTERISTICS
Item
Vcc for data retention
Data retention current
Data retention set-up time
Recovery time
Symbol
V
DR
I
DR
t
SDR
t
RDR
CS
1
≥Vcc-0.2V
1)
Vcc=3.0V, CS
1
≥Vcc-0.2V
1)
See data retention waveform
Test Condition
Min
2.0
-
0
5
Typ
-
0.2
-
-
Max
3.6
10
2)
-
-
Unit
V
µA
ms
1. CS
1
≥Vcc-0.2V,
CS
2
≥Vcc-0.2V(CS
1
controlled) or CS
2
≤0.2V(CS
2
controlled)
2. Industrial Prod
ucts = 15
µA
Revision 2.0
July 1999
Analog electronics
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