WED7GxxxATA33
DimmDrive Solid State ATA Flash Module
FEATURES
n
144 Pin SO-DIMM, JEDEC package
n
Plug-and-play solid state disk
n
NAND Flash memory technology by SanDisk
n
PC CARD ATA compatible - memory mapped or I/O operation
n
3.3 volt & 5.0 volt power supply operation
n
16MB - 768MB memory density
- (1GB - Q3/02)
n
Low Power Consumption
n
ECC error correction
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Supports true IDE mode
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8Kbyte data buffers
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Broad O/S support: DOS, Linux, Windows 3.X, Windows 95,
Windows NT4.0/5.0, Windows CE, others
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Compatible with major processors: x86, Media GX, PowerPC,
68K, MIPS, SHx, StrongArm, others
n
Full Hard Disk emulation and Boot capability
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Easy to use interface, JEDEC standard
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Supports power down commands and sleep modes
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Commercial temperature range 0C + 70C
n
Industrial temperature range -40C +85C
*PRELIMINARY
DESCRIPTION
The DimmDrive WED7GxxxATA33 is a high performance single
chip flash disk module available in 144 Pin SO-DIMM package.
The module is based on SanDisk NAND Flash technology and
utilizes the 128Mb, 256Mb, 512Mb or 1Gb memory components
to provide the maximum in module density.
The DimmDrive WED7GxxxATA33 utilizes a SanDisk Flash ChipSet
controller which is designed specifically for use as a Flash mass
storage controller for the SanDisk memory devices. This inter-
face allows a host computer to issue commands to read or write
blocks of memory in the Flash memory array. The intelligence to
manage the interface protocols, data storage and retrieval as well
as ECC, defect handling and diagnostics are controlled by this
device. Automatic power management and clock control is
handled by the controller as well.
The DimmDrive WED7GxxxATA33 module will have the same
functionality and capabilities of an intelligent ATA (IDE) disk
drive. An advantage of the on board Flash controller and it's ATA
command set, is the ease of software development by the user.
Once the device has been configured by the user, it appears to the
host as a standard ATA disk drive. Additional ATA commands
have been provided to enhance the system performance.
The on-board controller is a highly integrated solution and the
controller is designed to handle all intelligent operations, even the
rare cases when new defects arise and need to be mapped out or
replaced by a spare. The hardware performs the complicated
task of ECC detection and correction and will return good data to
the host. The controller manages all defects and errors and
makes the Flash memory appear as perfect memory to the host.
The DimmDrive WED7GxxxATA33 module also provides a more
cost effective solution to the traditional hard disk media. The
module is perfect for applications requiring upgradeability to
higher densities and for those applications with limited space
availability and power consumption requirements.
Unlike standard IDE drives, no cables or extra space is required.
The module has no moving parts providing significant reduction
in power consumption and increasing reliability. Simply insert the
module into a standard 144 Pin SO-DIMM socket and you then
have a bootable flash disk.
The DimmDrive WED7GxxxATA33 is available with memory
densities of 16MB to 768MB today with 1GB density available in
Q3/02.
1
White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
MODULE APPLICATIONS
Embedded systems
Internet Access Devices
Set Top Boxes
WEB Browser
Routers, Networking
WEB phones, car PC, DVD, HPC
Point-of-sale
Medical and Telecom
Other applications requiring embedded or solid state storage
*
This datasheet is preliminary, therefore all specifications are subject to change
without notice.
March 2002 Rev. A
ECO #XXXXX
WED7GxxxATA33
SIGNAL DESCRIPTION
Signal Name
DQ0-DQ7, DQ8-DQ15
CE0\, CE1\
OE\
WE\
A0-A10
Busy
RST
BVD1
BVD2
IOWR
IORD
REG
INPACK
IO16
Reserved
VCC
VSS
NC
Description
Data bus can either be 8-bits or 16-bits wide depending on selection of CE0\ and CE1\
CE1\ always selects the odd byte of the word. CE0\ accesses the even or odd byte depending on A0 and CE1\. For 8-bit
systems, CE0 is used and for 16-bit systems, both CE0\ and CE1\ are used. Both CE0\ and CE1\ should be decoded by the
logic to determine the memory window.
This is an output enable strobe generated by the host interface. It is used to read data from the Flash ChipSet in Memory Mode
and to read the CIS and configuration registers
The write enable pin is driven by the host and used for strobing data to the registers of the Flash ChipSet when the Flash
ChipSet is configured in the memory interface mode. It is also used for writing the configuration registers.
A0-A3 selects the basic registers of the controller to communicate to the module. This requires 16 bytes of host address space.
A0 is optional if CE0\ and CE1\ are combined to enable 16-bit wide register access.
The Busy signal is driven low when the product is accessing memory. When Busy is high, register access is allowed. After a
data transfer command is issued, this signal is used to signify that the host can transfer data.
When RST is high, the product is placed in a reset mode. This signal is only valid at power on.
This signal is driven high since a battery is not used with this product
This output line is always driven to a high state in Memory Mode since a batery is not required for this product
This signal is not used in the memory mode.
This signal is not used in the memory mode.
This signal is used during Memory Cycles to distinguish between common memory and register memory accesses. High for
common memory, low for attribute memory.
This signal is not used in the memory mode.
Optional test signals not used in the Memory Mapped Mode.
Pins are reserved for future expansion and must be left floating.
Power pins. All VCC pins must be connected.
Ground pins. All VSS pins must be connected.
No connect. Pin internally not connected.
BLOCK DIAGRAM
A0 - A10
CE0
6
n
2
1
D0 - D7
Data
SanDisk
Controller
D8 - D15
Control
NAND
Flash
CE1
BUSY
RST
Control signals used
in other modes (see
pin list)
WE
OE
March 2002 Rev. A
ECO #XXXXX
3
White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
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