IBM11D2325H2M x 3210/10, 5.0V, LC, Sn/PbMMDS45DSU-021023421. MMDS45DSU-021023421.
IBM11D2325H
2M x 32 DRAM Module
Features
• 72-Pin Single-In-Line Memory Module
• Performance:
-60
t
RAC
RAS Access Time
t
CAC
CAS Access Time
t
AA
Access Time From Address
t
RC
Cycle Time
t
HPC
EDO Mode Cycle Time
60ns
15ns
30ns
-6R
60ns
17ns
30ns
-70
70ns
20ns
35ns
•
•
•
•
•
•
•
•
•
•
•
104ns 104ns 124ns
25ns
25ns
30ns
• High Performance CMOS process
• Manufactured with 16Mb DRAMS (2M x 8)
Thin outline (.104”)
Single 5V
±
0.5V Power Supply
Low current consumption
All inputs & outputs are fully TTL & CMOS
compatible
Extended Data Out (EDO) access cycle
Refresh Modes: RAS-Only, CBR, and Hidden
Refresh
2098 refresh cycles distributed across 32ms
11/10 Addressing (Row/Column)
Optimized for use in byte-write, non-parity appli-
cations.
Tin/lead version only
DRAMs in TSOP package
Description
The IBM11D2325H is an 8MB 72-pin 4-byte single
in-line memory module (SIMM) manufactured using
EDO DRAMs. The module is organized as a 2Mx32
high speed memory array, and is configured as one
2Mx32 bank. The assembly is intended for use in
16, 32 and 64 bit applications. It is manufactured
with four 2Mx8 devices, each in a 400mil TSOP
package, and is compatible with applications that
support 11/10 (Row/Column) addressing.
The use of EDO DRAMs allows for a reduction in
Page Mode cycle time from 40ns (Fast Page) to
25ns (EDO, 60ns/6Rns sort). The use of TSOP
packages allows tight SIMM spacing (.3” on center).
Input loading is consistent with 4Mb-based assem-
blies due to the addition of discrete capacitors maxi-
mizing compatibility at the system-level.
The IBM 72-Pin SIMMs provide a high performance,
flexible 4-byte interface in a 4.25” long footprint.
Card Outline
1
36 37
72
75H1698
SA14-4337-01
Revised 6/96
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 1 of 21
IBM11D2325H
2M x 32 DRAM Module
Pin Description
RAS0, RAS2
Row Address Strobe
CAS0 - CAS3 Column Address Strobe
WE
A0 - A10
DQ0-7, 9-16,
18-25, 27-34
V
CC
V
SS
NC
PD1 - PD4
Read/write Input
Address Inputs
Data Input/output
Power (+5V)
Ground
No Connect
Presence Detects
Pinout
Pin#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Name
V
SS
DQ0
DQ18
DQ1
DQ19
DQ2
DQ20
DQ3
DQ21
V
CC
NC
A0
A1
A2
A3
A4
A5
A6
A10
DQ4
DQ22
DQ5
DQ23
DQ6
Pin#
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
Name
DQ24
DQ7
DQ25
A7
NC
V
CC
A8
A9
NC
RAS2
NC
NC
NC
NC
V
SS
CAS0
CAS2
CAS3
CAS1
RAS0
NC
NC
WE
NC
Pin#
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
Name
DQ9
DQ27
DQ10
DQ28
DQ11
DQ29
DQ12
DQ30
DQ13
DQ31
V
CC
DQ32
DQ14
DQ33
DQ15
DQ34
DQ16
NC
PD1
PD2
PD3
PD4
NC
V
SS
1. DQ numbering is compatible with non-parity (x32) version.
Ordering Information
Part Number
IBM11D2325H-60
IBM11D2325H-6R
IBM11D2325H-70
IBM11D2325H-60T
IBM11D2325H-6RT
IBM11D2325H-70T
2M x 32
Organization
Speed
60ns
6Rns
70ns
60ns
6Rns
70ns
11/10
Sn/Pb
4.25” x 1” x .104”
1
Addr.
Leads
Dimensions
Notes
2
1, 2
2
1. 6Rns speed sort has t
CAC
of 17ns
2. DRAM package designator appended to speed portion of part number on assemblies beginning with DRAM die rev E.
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
75H1698
SA14-4337-01
Revised 6/96
Page 2 of 21
IBM11D2325H
2M x 32 DRAM Module
Block Diagram
RAS0
RAS
RAS
WE
RAS2
RAS
WE
RAS
WE
WE
A0 - A10
CAS0
WE
A0 - A10
U1
A0 - A10
U2
A0 - A10
U3
A0 - A10
U4
CAS
CAS1
DQ
CAS
CAS2
DQ
CAS
CAS3
DQ
CAS
OE
OE
OE
OE
DQ
DQ0 - DQ7
DQ9 - DQ16
DQ18 - DQ25
DQ27 - DQ34
75H1698
SA14-4337-01
Revised 6/96
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 3 of 21
IBM11D2325H
2M x 32 DRAM Module
Truth Table
Function
Standby
Read
Early-Write
EDO Mode - Read:
1st Cycle
Subsequent Cycles
EDO Mode - Write:
1st Cycle
Subsequent Cycles
RAS-Only Refresh
CAS-Before-RAS Refresh
Read
Hidden Refresh
Write
L→H→L
L
L
Row
Col
Data In
RAS
H
L
L
L
L
L
L
L
H→L
L→H→L
CAS
H→X
L
L
H→L
H→L
H→L
H→L
H
L
L
WE
X
H
L
H
H
L
L
X
H
H
Row
Address
X
Row
Row
Row
N/A
Row
N/A
Row
X
Row
Column
Address
X
Col
Col
Col
Col
Col
Col
N/A
X
Col
All DQ bits
High Impedance
Valid Data Out
Valid Data In
Valid Data Out
Valid Data Out
Valid Data In
Valid Data In
High Impedance
High Impedance
Data Out
Presence Detect
2M x 32
Pin
-60 / 6R
PD1
PD2
PD3
PD4
1.
NC= OPEN
,
V
ss =
GND
NC
NC
NC
NC
-70
NC
NC
V
SS
NC
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
75H1698
SA14-4337-01
Revised 6/96
Page 4 of 21
IBM11D2325H
2M x 32 DRAM Module
Absolute Maximum Ratings
Symbol
V
CC
V
IN
V
OUT
T
OPR
T
STG
P
D
I
OUT
Parameter
Power Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
Storage Temperature
Power Dissipation
Short Circuit Output Current
Rating
-1.0 to +7.0
-0.5 to min (V
CC
+ 0.5, 7.0)
-0.5 to min (V
CC
+ 0.5, 7.0)
0 to +70
-55 to +125
1.98
50
Units
V
V
V
°C
°C
W
mA
Notes
1
1
1
1
1
1
1
1. Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only, and device functional
operation at or above the conditions indicated is not implied. Exposure to absolute maximum rating conditions for extended peri-
ods may affect reliability.
Recommended DC Operating Conditions
Symbol
V
CC
V
IH
V
IL
Supply Voltage
Input High Voltage
Input Low Voltage
Parameter
(T
A
= 0 to 70
°
C)
Min
4.5
2.4
-0.5
Typ
5.0
—
—
Max
5.5
V
CC
+ 0.5
0.8
Units
V
V
V
Notes
1
1, 2
1, 2
1. All voltages referenced to V
SS
.
2. V
IH
may overshoot to V
CC
+ 2.0V for pulse widths of
≤
4.0ns (or V
CC
+ 1.0V for
≤
8.0ns). Additionally, V
IL
may undershoot to -2.0V
for pulse widths
≤
4.0ns (or -1.0V for
≤
8.0ns). Pulse widths measured at 50% points with amplitude measured peak to DC refer-
ence.
Capacitance
Symbol
C
I1
C
I2
C
I3
C
I4
C
I/O
(T
A
= 0 to +70°C, V
CC
= 5.0V
±
0.5V)
Parameter
2M x 32
Max
30
24
17
38
15
Units
pF
pF
pF
pF
pF
Input Capacitance (A0-A10)
Input Capacitance (RAS)
Input Capacitance (CAS)
Input Capacitance (WE)
Output Capacitance (All DQ)
75H1698
SA14-4337-01
Revised 6/96
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 5 of 21