Preliminary Datasheet
LPA8302
3-Walts Mono Filter-free Class-D Audio Power Amplifier
General Description
The LPA8302 is a high efficiency, 3W mono class-D
audio power amplifier. A low noise, filterless PWM
architecture eliminates the output filter, reducing
external component count, system cost, and simplifying
design.
Operating in a single 5V supply, LPA8302 is capable of
driving 4Ω
speaker load at a continuous average output
of 3W/10% THD+N or 2W/1% THD+N. The LPA8302
has high efficiency with speaker load compared to a
typical class D amplifier. With a 3.6V supply driving an
8Ω
speaker, the efficiency for a 400mW power level is
88%.In cellular handsets, the earpiece, speaker phone,
and melody ringer can each be driven by the LPA8302.
The gain of LPA8302 is externally configurable which
allows independent gain control from multiple sources
by summing signals from seperated sources.
The LPA8302 is available in space-saving MSOP-8
packages.
Features
Unique
Modulation
Scheme
Reduces
EMI
Emissions
Efficiency at 3.6V With an 8-Ω
Speaker:
−
88% at 400 mW
−
80% at 100 mW
Low 2.4-mA Quiescent Current
0.5-µA Shutdown Current
2.5V to 5.5V Wide Supply Voltage
Shutdown Pin has 1.8V Compatible Thresholds
Optimized PWM Output Stage Eliminates LC
Output Filter
Improved PSRR (−72
dB) Eliminates Need for a
Voltage Regulator
Fully Differential Design Reduces RF Rectification
and Eliminates Bypass Capacitor
Improved CMRR Eliminates Two Input Coupling
Capacitors
Internally Generated 250-kHz Switching
Frequency
Integrated Pop and Click Suppression Circuitry
MSOP-8 package
RoHS compliant and 100% lead(Pb)-free
Order Information
LPA8302
□ □
□
F: Pb-Free
Package Type
MS: MSOP-8
Typical Application Circuit
C1
DIFFERENTIAL
INPUT
INTERNAL
OSCILLATOR
R1
IN-
-
+
IN+
BIAS
CIRCUITRY
GND
PWM
H-
BRIDGE
VO+
VO-
VDD
TO BATTERY
CS
C1
R1
SHUTDOWN
Applications
PMP,PSP, Game,
Data-Bank
Cellular and Smart mobile phone
PDA/DSC
FILTER-FREE CLASS D
Marking Information
Please see website.
LPA8302–02
May.-2010
Email:
marketing@lowpowersemi.com
www.lowpowersemi.com
Page 1 of 14
Preliminary Datasheet
LPA8302
Functional Pin Description
P ac ka ge Typ e
P in C o n f ig u r a t io n s
MSOP-8
TOP VIEW
SHUTDOWN
NC
IN+
IN-
1
2
3
4
8
7
6
5
VO-
GND
VDD
LPA8302
9
GND
VO+
Pin Description
Pin
SHUTDOWN
NC
IN+
IN-
VO+
VDD
GND
VO-
PIN
1
2
3
4
5
6
7
8
Shutdown terminal (active low logic)
No internal connection
Positive differential input
Negative differential input
Negative BTL output
Power supply
High-current ground
Positive BTL output
DESCRIPTION
Function Block Diagram
GAIN=
150KΩ
R1
GAIN=2V/V
VDD
VDD
GATE
DRIVE
IN-
150KΩ
+
+ -
-
-
+
+
-
+
-
DELITCH
LOGIC
VO-
IN+
150KΩ
TTL
INPUT
BUFFER
+
-
DELITCH
LOGIC
GATE
DRIVE
VO+
SHUTDOWN
SD
300KΩ
BIASES
AND
REFERENCE
RAMP
GENERATOR
STARTUP
PROTECTION
LOGIC
OC
DETECT
GND
LPA8302–02
May.-2010
Email:
marketing@lowpowersemi.com
www.lowpowersemi.com
Page 2 of 14
Preliminary Datasheet
LPA8302
Absolute Maximum Ratings
Input Voltage to GND (VINA, VINB) --------------------------------------------------------------------------------------------------------------- 6V
Adapter Voltage to GND (VADP) -------------------------------------------------------------------------------------------------------- 0.3V to 6V
Supply Voltage, V
DD
--------------------------------------------------------------------------------------------------------------
Voltage at Any Input Pin ------------------------------------------------------------------------------------------------
-0.3 V to 6V
-0.3 V to V
DD
+0.3V
150°C
Junction Temperature, TJMAX -----------------------------------------------------------------------------------------------------------
Storage Temperature Rang, T
stg
ESD Susceptibility
-----------------------------------------------------------------------------------------
-65°C to 150°C
2kV
260°C
47°C/W
----------------------------------------------------------------------------------------------------------------------
Lead temperature
1,6 mm (1/16 inch) from case for 10 seconds
------------------------------------------------------------
Thermal Resistance
θ
JA
(TDFN)
----------------------------------------------------------------------------------------------------
LPA8302–02
May.-2010
Email:
marketing@lowpowersemi.com
www.lowpowersemi.com
Page 3 of 14
Preliminary Datasheet
LPA8302
Electrical Characteristics
Symbol
Parameter
Output offset voltage
VOS
PSRR
CMRR
(measured differentially)
Power supply rejection ration
Common mode rejection ratio
Conditions
Vi=0V,Av=2V/V,VDD=2.5V to 5.5V
VDD=2.5V to 5.5V
VDD=2.5V to 5.5V,Vic=VDD/2 to 0.5V,Vin=VDd/2 to
Vdd-0.8V
VDD=5.5V, no load
IQ
Quiescent current
VDD=3.6V, no load
VDD=2.5V, no load
ISHDN
ILIM
Shutdown Current
P-Channel Current Limit
Static drain-source
on-state resistance
Switching frequency
VDD=5.5V, no load
VDD=3.6V, no load
VDD=2.5V, no load
VDD=2.5V to 5.5V
THD+N=10%,
F=1KHz,RL=4
VDD=5.0V
VDD=3.6V
VDD=2.5V
THD+N=1%,
F=1KHz,RL=4
PO
Output power
THD+N=10%,
F=1KHz,RL=8
VDD=5.0V
VDD=3.6V
VDD=2.5V
VDD=5.0V
VDD=3.6V
VDD=2.5V
THD+N=1%,
F=1KHz,RL=8
VDD=3.6V,Inputs
Supply ripple rejection ratio
kSVR
CMRR
Zt
Common mode rejection ratio
Start-up time from shutdown
ac-grounded
with Ci=2uF
VDD=3.6V,
Vic=1Vpp
VDD=3.6
VDD=5.0V
VDD=3.6V
VDD=2.5V
F=217Hz,V9ripple)=200m
Vpp
F=217Hz
200
VSHDN=0.35V, VDD=2.5V to 5.5V
LPA8302
Min.
Typ.
5
-80
-77
4.52
2.40
2.06
0.5
1
400
500
700
250
3.0
1.3
0.64
2.15
1.06
0.46
1.67
0.79
0.39
1.36
0.64
0.32
W
W
W
W
300
KHz
m
µA
A
mA
Max.
25
Unit
mV
dB
dB
RDS(ON)
F(SW)
-60
dB
-55
11.5
dB
mS
LPA8302–02
May.-2010
Email:
marketing@lowpowersemi.com
www.lowpowersemi.com
Page 4 of 14
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