PI6C39911-2J datasheet, PDF - EEWORLD Datasheet

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PI6C39911-2J: Description3.3V High Speed LVTTL or Balanced Output Programmable Skew Clock Buffer - SuperClock; Categorylogic logic; File Size261KB，11 Pages; ManufacturerPericom Semiconductor Corporation (Diodes Incorporated); Websitehttps://www.diodes.com/

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PI6C39911-2J Overview

3.3V High Speed LVTTL or Balanced Output Programmable Skew Clock Buffer - SuperClock

PI6C39911-2J Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	Pericom Semiconductor Corporation (Diodes Incorporated)
Parts packaging code	QFJ
package instruction	QCCJ, LDCC32,.5X.6
Contacts	32
Reach Compliance Code	compli
ECCN code	EAR99
Is Samacsys	N
series	6C
Input adjustment	STANDARD
JESD-30 code	R-PQCC-J32
JESD-609 code	e0
length	13.97 mm
Logic integrated circuit type	PLL BASED CLOCK DRIVER
MaximumI(ol)	0.035 A
Humidity sensitivity level	3
Number of functions	1
Number of inverted outputs
Number of terminals	32
Actual output times	4
Maximum operating temperature	70 °C
Minimum operating temperature
Package body material	PLASTIC/EPOXY
encapsulated code	QCCJ
Encapsulate equivalent code	LDCC32,.5X.6
Package shape	RECTANGULAR
Package form	CHIP CARRIER
Peak Reflow Temperature (Celsius)	225
power supply	3.3 V
Prop。Delay @ Nom-Su	0.3 ns
propagation delay (tpd)	0.3 ns
Certification status	Not Qualified
Same Edge Skew-Max（tskwd）	0.8 ns
Maximum seat height	3.556 mm
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	3 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	BICMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	J BEND
Terminal pitch	1.27 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	10
width	11.43 mm
minfmax	133 MHz
Base Number Matches	1

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CCQ

REF

GND

REF

Phase

Freq.

DET

Filter

VCO and

Time Unit

Generator

3F1

4F0

4F1

CCQ

CCN

4Q1

4Q0

GND

32 31

TEST

2F1

3F0

CCN

3Q1

3Q0

1F0

1F1

1Q0

1Q1

2Q1

2Q0

21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321

PI6C39911

3.3V High Speed LVTTL or Balanced Output

Programmable Skew Clock Buffer -

SuperClock

Features

• All output pair skew <100ps typical (250 Max.)

• 12.5 MHz to 133 MHz output operation

• 3.125 MHz to 133 MHz input operation (input as low as 3.125

MHz for 4x operation, or 6.25 MHz for 2x operation)

• User-selectable output functions

— Selectable skew to 18ns

— Inverted and non-inverted

— Operation at ½ and ¼ input frequency

— Operation at 2X and 4X input frequency

• Zero input-to-output delay

• 50% duty-cycle outputs

• Inputs are 5V Tolerant

• LVTTL outputs drive 50-Ohm terminated lines

• Operates from a single 3.3V supply

• Low operating current

• 32-pin PLCC package

• Jitter < 200ps peak-to-peak (< 25ps RMS)

Description

The PI6C39911 offers selectable control over system clock func-

tions. These multiple-output clock drivers provide the system

integrator with functions necessary to optimize the timing

of high-performance computer systems. Eight individual drivers,

arranged as four pairs of user-controllable outputs, can each drive

terminated transmission lines with impedances as low as 50-Ohms

while delivering minimal and specified output skews and full-swing

logic levels.

Each output can be hardwired to one of nine skews or function

configurations. Delay increments of 0.7ns to 1.5ns are determined

by the operating frequency with outputs able to skew up to ±6 time

units from their nominal “zero” skew position. The completely

integrated PLL allows external load and transmission line delay

effects to be canceled. The user can create output-to-output skew

of up to ±12 time units.

Divide-by-two and divide-by-four output functions are provided

for additional flexibility in designing complex clock systems. When

combined with the internal PLL, these divide functions allow distri-

bution of a low-frequency clock that can be multiplied by two or four

at the clock destination. This feature allows flexibility and simpli-

fies system timing distribution design for complex high-speed

systems.

Logic Block Diagram

Test

Pin Configuration

4F0

4F1

Select Inputs

(three level)

4Q0

4Q1

Skew

Select

Matrix

3Q0

3Q1

2Q0

2Q1

32 Pin

3F0

3F1

2F0

2F1

2F0

GND

1F1

1F0

CCN

1Q0

1Q1

GND

14 15 16 17 18 19

PS8497E

09/13/02

PI6C39911-2J Related Products

	PI6C39911-2J	PI6C39911	PI6C39911-5J	PI6C399111J
Description	3.3V High Speed LVTTL or Balanced Output Programmable Skew Clock Buffer - SuperClock	3.3V High Speed LVTTL or Balanced Output Programmable Skew Clock Buffer - SuperClock	3.3V High Speed LVTTL or Balanced Output Programmable Skew Clock Buffer - SuperClock	3.3V High Speed LVTTL or Balanced Output Programmable Skew Clock Buffer - SuperClock
Is it lead-free?	Contains lead	Contains lead	Contains lead	-
Is it Rohs certified?	incompatible	incompatible	incompatible	-
Maker	Pericom Semiconductor Corporation (Diodes Incorporated)	Pericom Semiconductor Corporation (Diodes Incorporated)	Pericom Semiconductor Corporation (Diodes Incorporated)	-
Parts packaging code	QFJ	QFJ	QFJ	-
package instruction	QCCJ, LDCC32,.5X.6	QCCJ,	QCCJ, LDCC32,.5X.6	-
Contacts	32	32	32	-
Reach Compliance Code	compli	compliant	compli	-
ECCN code	EAR99	EAR99	EAR99	-
series	6C	6C	6C	-
Input adjustment	STANDARD	STANDARD	STANDARD	-
JESD-30 code	R-PQCC-J32	R-PQCC-J32	R-PQCC-J32	-
JESD-609 code	e0	e0	e0	-
Logic integrated circuit type	PLL BASED CLOCK DRIVER	PLL BASED CLOCK DRIVER	PLL BASED CLOCK DRIVER	-
Humidity sensitivity level	3	3	3	-
Number of functions	1	1	1	-
Number of terminals	32	32	32	-
Actual output times	4	8	4	-
Maximum operating temperature	70 °C	70 °C	70 °C	-
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	-
encapsulated code	QCCJ	QCCJ	QCCJ	-
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	-
Package form	CHIP CARRIER	CHIP CARRIER	CHIP CARRIER	-
Peak Reflow Temperature (Celsius)	225	240	225	-
Certification status	Not Qualified	Not Qualified	Not Qualified	-
Same Edge Skew-Max（tskwd）	0.8 ns	1.2 ns	1 ns	-
Maximum supply voltage (Vsup)	3.6 V	3.63 V	3.6 V	-
Minimum supply voltage (Vsup)	3 V	2.97 V	3 V	-
Nominal supply voltage (Vsup)	3.3 V	3.3 V	3.3 V	-
surface mount	YES	YES	YES	-
Temperature level	COMMERCIAL	COMMERCIAL	COMMERCIAL	-
Terminal surface	Tin/Lead (Sn/Pb)	TIN LEAD	Tin/Lead (Sn/Pb)	-
Terminal form	J BEND	J BEND	J BEND	-
Terminal location	QUAD	QUAD	QUAD	-
Maximum time at peak reflow temperature	10	NOT SPECIFIED	10	-
minfmax	133 MHz	133 MHz	133 MHz	-

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