S29JL032H
32 Mbit (4 M x 8-Bit/2 M x 16-Bit), 3 V
Simultaneous Read/Write Flash
Distinctive Characteristics
Simultaneous Read/Write Operations
– Data can be continuously read from one bank while executing
erase/program functions in another bank.
– Zero latency between read and write operations
Multiple Bank Architecture
– Four bank architectures available (refer to
Table on page 11).
Boot Sectors
– Top and bottom boot sectors in the same device
– Any combination of sectors can be erased
Manufactured on 0.13 µm Process Technology
Secured Silicon Sector:
Extra 256 Byte sector
–
Customer lockable:
One-time programmable only. Once locked,
data cannot be changed
Zero Power Operation
– Sophisticated power management circuits reduce power
consumed during inactive periods to nearly zero.
Compatible with JEDEC standards
– Pinout and software compatible with single-power-supply flash
standard
Package options
48-pin TSOP
Performance Characteristics
High Performance
– Access time as fast as 60 ns
– Program time: 4 µs/word typical using accelerated programming
function
Ultra Low Power Consumption (typical values)
– 2 mA active read current at 1 MHz
– 10 mA active read current at 5 MHz
General Description
The S29JL032H is a 32 megabit, 3.0 volt-only flash memory device, organized as 2,097,152 words of 16 bits each or 4,194,304
bytes of 8 bits each. Word mode data appears on DQ15–DQ0; byte mode data appears on DQ7–DQ0. The device is designed to
be programmed in-system with the standard 3.0 volt V
CC
supply, and can also be programmed in standard EPROM programmers.
The device is available with an access time of 60, 70, or 90 ns and is offered in a 48-pin TSOP package. Standard control pins—
chip enable (CE#), write enable (WE#), and output enable (OE#)—control normal read and write operations, and avoid bus
contention issues.
The device requires only a
single 3.0 volt power supply
for both read and write functions. Internally generated and regulated
voltages are provided for the program and erase operations.
Cypress Semiconductor Corporation
Document Number: 002-01186 Rev. *A
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Cycling Endurance: 1 million cycles per sector typical
Data Retention: 20 years typical
Architectural Advantages
– 200 nA in standby or automatic sleep mode
Software Features
Supports Common Flash Memory Interface (CFI)
Erase Suspend/Erase Resume
– Suspends erase operations to read data from, or program data to,
a sector that is not being erased, then resumes the erase
operation.
Data# Polling and Toggle Bits
– Provides a software method of detecting the status of program or
erase cycles
Unlock Bypass Program Command
– Reduces overall programming time when issuing multiple
program command sequences
Hardware Features
Ready/Busy# Output (RY/BY#)
– Hardware method for detecting program or erase cycle
completion
Hardware Reset Pin (RESET#)
– Hardware method of resetting the internal state machine to the
read mode
WP#/ACC Input Pin
– Write protect (WP#) function protects the two outermost boot
sectors regardless of sector protect status
– Acceleration (ACC) function accelerates program timing
Sector Protection
– Hardware method to prevent any program or erase operation
within a sector
– Temporary Sector Unprotect allows changing data in protected
sectors in-system
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•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised December 08, 2015
S29JL032H
Contents
1.
1.1
2.
3.
3.1
3.2
4.
5.
6.
7.
8.
8.1
8.2
8.3
8.4
8.5
8.6
8.7
8.8
8.9
8.10
8.11
8.12
8.13
8.14
9.
10.
10.1
10.2
10.3
10.4
Simultaneous Read/Write Operations with Zero
Latency
......................................................................... 3
S29JL032H Features ..................................................... 3
Product Selector Guide
............................................... 3
14.1 CMOS Compatible ........................................................ 38
14.2 Zero-Power Flash ......................................................... 39
15.
16.
Test Conditions
........................................................... 40
Key To Switching Waveforms
.................................... 41
Block Diagram..............................................................
4
4 Bank Device................................................................ 4
2 Bank Device................................................................ 5
Connection Diagrams..................................................
6
Pin Description.............................................................
6
Logic Symbol
............................................................... 7
Ordering Information
................................................... 7
Device Bus Operations................................................
8
Word/Byte Configuration................................................ 9
Requirements for Reading Array Data........................... 9
Writing Commands/Command Sequences.................. 10
Simultaneous Read/Write Operations with
Zero Latency ................................................................ 10
Standby Mode.............................................................. 10
Automatic Sleep Mode................................................. 11
RESET#: Hardware Reset Pin..................................... 11
Output Disable Mode ................................................... 11
Autoselect Mode .......................................................... 16
Sector/Sector Block Protection and Unprotection........ 17
Write Protect (WP#) ..................................................... 19
Temporary Sector Unprotect........................................ 19
Secured Silicon Sector Flash Memory Region ............ 21
Hardware Data Protection............................................ 22
Common Flash Memory Interface (CFI)
................... 23
10.5
10.6
10.7
10.8
Command Definitions................................................
26
Reading Array Data ..................................................... 26
Reset Command .......................................................... 26
Autoselect Command Sequence ................................. 26
Enter Secured Silicon Sector/Exit Secured
Silicon Sector Command Sequence ............................ 27
Byte/Word Program Command Sequence................... 27
Chip Erase Command Sequence ................................ 28
Sector Erase Command Sequence ............................. 28
Erase Suspend/Erase Resume Commands ................ 30
Write Operation Status
..............................................
DQ7: Data# Polling ......................................................
RY/BY#: Ready/Busy#.................................................
DQ6: Toggle Bit I .........................................................
DQ2: Toggle Bit II ........................................................
Reading Toggle Bits DQ6/DQ2....................................
DQ5: Exceeded Timing Limits .....................................
DQ3: Sector Erase Timer.............................................
11.
11.1
11.2
11.3
11.4
11.5
11.6
11.7
12.
13.
14.
Absolute Maximum Ratings......................................
37
Operating Ranges
...................................................... 38
DC Characteristics.....................................................
38
Page 2 of 58
Document Number: 002-01186 Rev. *A
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17.
17.1
17.2
17.3
17.4
17.5
17.6
18.
19.
32
32
33
34
35
36
36
37
AC Characteristics......................................................
41
Read-Only Operations .................................................. 41
Hardware Reset (RESET#)........................................... 43
Word/Byte Configuration (BYTE#) ................................ 44
Erase and Program Operations .................................... 45
Temporary Sector Unprotect......................................... 49
Alternate CE# Controlled Erase and Program
Operations ....................................................................50
Erase and Programming Performance
..................... 51
TSOP Pin Capacitance................................................
52
20. Physical Dimensions
.................................................. 53
20.1 TS 048—48-Pin Standard TSOP .................................. 53
21. Revision History..........................................................
54
21.1 Revision A0 (May 21, 2004).......................................... 54
21.2 Revision A1 (August 5, 2004) ....................................... 54
21.3 Revision A2 (March 10, 2005) ...................................... 54
21.4 Revision B0 (September 21, 2005)............................... 54
21.5 Revision B1 (November 28, 2005)................................ 54
21.6 Revision B2 (March 13, 2006) ...................................... 55
21.7 Revision B3 (May 19, 2006).......................................... 55
21.8 Revision B4 (June 7, 2007)........................................... 55
21.9 Revision B5 (August 10, 2007) ..................................... 55
21.10Revision B6 (March 7, 2008) ........................................ 55
21.11Revision B7 (July 7, 2008)............................................ 55
21.12Revision B8 (August 31, 2009)..................................... 55
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S29JL032H
1.
Simultaneous Read/Write Operations with Zero Latency
The Simultaneous Read/Write architecture provides
simultaneous operation
by dividing the memory space into separate banks
(see
Table on page 11).
Sector addresses are fixed, system software can be used to form user-defined bank groups.
During an Erase/Program operation, any of the non-busy banks may be read from. Note that only two banks can operate
simultaneously. The device can improve overall system performance by allowing a host system to program or erase in one bank,
then immediately and simultaneously read from the other bank, with zero latency. This releases the system from waiting for the
completion of program or erase operations.
The S29JL032H can be organized as both a top and bottom boot sector configuration.
1.1
The
Secured Silicon Sector
is an extra 256 byte sector capable of being permanently locked by the customer. The Secured Silicon
Customer Indicator Bit (DQ6) is permanently set to 1 if the part has been locked and is 0 if lockable.
Customers may utilize the Secured Silicon Sector as bonus space, reading and writing like any other flash sector, or may
permanently lock their own code there.
DMS (Data Management Software)
allows systems to easily take advantage of the advanced architecture of the simultaneous
read/write product line by allowing removal of EEPROM devices. DMS will also allow the system software to be simplified, as it will
perform all functions necessary to modify data in file structures, as opposed to single-byte modifications. To write or update a
particular piece of data (a phone number or configuration data, for example), the user only needs to state which piece of data is to be
updated, and where the updated data is located in the system. This is an advantage compared to systems where user-written
software must keep track of the old data location, status, logical to physical translation of the data onto the Flash memory device (or
memory devices), and more. Using DMS, user-written software does not need to interface with the Flash memory directly. Instead,
the user's software accesses the Flash memory by calling one of only six functions.
The device offers complete compatibility with the
JEDEC 42.4 single-power-supply Flash command set standard.
Commands
are written to the command register using standard microprocessor write timings. Reading data out of the device is similar to reading
from other Flash or EPROM devices.
The host system can detect whether a program or erase operation is complete by using the device
status bits:
RY/BY# pin, DQ7
(Data# Polling) and DQ6/DQ2 (toggle bits). After a program or erase cycle has been completed, the device automatically returns to
the read mode.
The
sector erase architecture
allows memory sectors to be erased and reprogrammed without affecting the data contents of other
sectors. The device is fully erased when shipped from the factory.
Hardware data protection
measures include a low V
CC
detector that automatically inhibits write operations during power
transitions. The
hardware sector protection
feature disables both program and erase operations in any combination of the sectors
of memory. This can be achieved in-system or via programming equipment.
The device offers two power-saving features. When addresses have been stable for a specified amount of time, the device enters
the
automatic sleep mode.
The system can also place the device into the
standby mode.
Power consumption is greatly reduced in
both modes.
2. Product Selector Guide
Part Number
Speed Option
Max Access Time (ns), t
ACC
CE# Access (ns), t
CE
OE# Access (ns), t
OE
Standard Voltage Range: V
CC
= 3.0–3.6 V
Standard Voltage Range: V
CC
= 2.7–3.6 V
60
60
25
60
70
70
70
30
90
90
90
35
S29JL032H
Document Number: 002-01186 Rev. *A
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S29JL032H Features
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Page 3 of 58
S29JL032H
3. Block Diagram
3.1
4 Bank Device
V
CC
V
SS
Document Number: 002-01186 Rev. *A
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OE#
BYTE#
Mux
Bank 1
A20–A0
Bank 1 Address
Y-gate
X-Decoder
A20–A0
RY/BY#
Bank 2 Address
Bank 2
X-Decoder
A20–A0
RESET#
WE#
CE#
BYTE#
WP#/ACC
STATE
CONTROL
&
COMMAND
REGISTER
Status
DQ15–DQ0
DQ15–DQ0
DQ15–DQ0
Control
Mux
A20–A0
X-Decoder
Bank 3
X-Decoder
Bank 4
A20–A0
Bank 4 Address
Mux
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DQ15–DQ0
Bank 3 Address
Y-gate
DQ15–DQ0
DQ0–DQ15
Page 4 of 58
S29JL032H
3.2
V
CC
V
SS
2 Bank Device
OE# BYTE#
Document Number: 002-01186 Rev. *A
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Y-Decoder
A20–A0
Upper Bank Address
Upper Bank
Latches and Control Logic
RY/BY#
A20–A0
X-Decoder
RESET#
WE#
CE#
BYTE#
WP#/ACC
STATE
CONTROL
&
COMMAND
REGISTER
Status
DQ15–DQ0
A20–A0
DQ15–DQ0
Control
A20–A0
X-Decoder
Lower Bank
A20–A0
Lower Bank Address
OE# BYTE#
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Latches and
Control Logic
Y-Decoder
DQ15–DQ0
DQ15–DQ0
Page 5 of 58
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