S71GL512NB0BAWEK2 datasheet, PDF

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S71GL512NB0BAWEK2: DescriptionMemory Circuit, 32MX16, CMOS, PBGA84, 9 X 12 MM, 1.20 MM HIEGHT, FBGA-84; Categorystorage storage; File Size3MB，147 Pages; ManufacturerSPANSION; Websitehttp://www.spansion.com/

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S71GL512NB0BAWEK2 Overview

Memory Circuit, 32MX16, CMOS, PBGA84, 9 X 12 MM, 1.20 MM HIEGHT, FBGA-84

S71GL512NB0BAWEK2 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	SPANSION
Objectid	2087609587
Parts packaging code	BGA
package instruction	TFBGA,
Contacts	84
Reach Compliance Code	compliant
compound_id	6460014
Other features	PSRAM IS ORGANIZED AS 2M X 16
JESD-30 code	R-PBGA-B84
JESD-609 code	e0
length	12 mm
memory density	536870912 bit
Memory IC Type	MEMORY CIRCUIT
memory width	16
Number of functions	1
Number of terminals	84
word count	33554432 words
character code	32000000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-25 °C
organize	32MX16
Package body material	PLASTIC/EPOXY
encapsulated code	TFBGA
Package shape	RECTANGULAR
Package form	GRID ARRAY, THIN PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
Certification status	Not Qualified
Maximum seat height	1.2 mm
Maximum supply voltage (Vsup)	3.1 V
Minimum supply voltage (Vsup)	2.7 V
Nominal supply voltage (Vsup)	3 V
surface mount	YES
technology	CMOS
Temperature level	OTHER
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	BALL
Terminal pitch	0.8 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED
width	9 mm

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S71GL512NB0/S71GL256NB0/

S71GL128NB0

Stacked Multi-chip Product (MCP)

512/256/128 Megabit (32/16/8 M x 16-bit) CMOS 3.0 Volt-only

MirrorBit

Page-mode Flash Memory with

32 Megabit (2M x 16-bit) pSRAM

ADVANCE

INFORMATION

Distinctive Characteristics

MCP Features

Power supply voltage of 2.7 to 3.1V

High Performance

90 ns access time (S71GL128N, S71GL256N)

100 ns access time (S71GL512N)

25 ns page read times

Packages:

— 9.0 x 12.0 mm x 1.2 mm FBGA (TLD084) (S71GL512N)

— 8.0 x 11.6 mm x 1.2 mm FBGA (TLA084) (S71GL128N, S71GL256N)

Operating Temperature

— -25°C to +85°C (Wireless)

— -40°C to +85°C (Industrial)

General Description

The S71GL Series is a product line of stacked Multi-chip Product (MCP) packages

and consists of

One Flash memory die

one pSRAM

The products covered by this document are listed in the table below. For details

about their specifications, please refer to the individual constituent datasheets

for further details.

Flash Memory Density

512 Mb

128 Mb

pSRAM Density

64 Mb

32 Mb

16 Mb

S71GL512NB0

S71GL256NB0

S71GL128NB0

256 Mb

128 Mb

Publication Number

S71GL512_256_128NB0_00

Revision

Amendment

Issue Date

December 7, 2004

This document contains information on a product under development at Spansion LLC. The information is intended to help you evaluate this product. Spansion LLC

reserves the right to change or discontinue work on this proposed product without notice.

A d v a n c e

I n f o r m a t i o n

S71GL512NB0/S71GL256NB0/S71GL128NB0

General Description . . . . . . . . . . . . . . . . . . . . . . . . 1

Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 4

MCP Block Diagram (128Mb Flash + 32Mb pSRAM) ..................................5

MCP Block Diagram (256Mb Flash + 32Mb pSRAM) .................................5

MCP Block Diagram (512Mb Flash + 32Mb pSRAM) ..................................6

Logical Inhibit ................................................................................................... 45

Power-Up Write Inhibit ............................................................................... 45

Common Flash Memory Interface (CFI) . . . . . . . 45

Table 6. CFI Query Identification String ................................

Table 7. System Interface String..........................................

Table 8. Device Geometry Definition.....................................

Table 9. Primary Vendor-Specific Extended Query ..................

Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . 7

512 Mb Flash + 32 Mb pSRAM Pinout .............................................................7

256 Mb Flash + 32 Mb pSRAM Pinout ............................................................8

128 Mb Flash + 32 Mb pSRAM Pinout .............................................................9

128 Mb Flash + 32 Mb pSRAM Pinout (S71GL128NB0 Only) .................. 10

Command Definitions . . . . . . . . . . . . . . . . . . . . . . 49

Reading Array Data ...........................................................................................50

Reset Command .................................................................................................50

Autoselect Command Sequence ................................................................... 50

Enter Secured Silicon Sector/Exit Secured Silicon

Sector Command Sequence ............................................................................. 51

Word Program Command Sequence ........................................................... 51

Unlock Bypass Command Sequence ........................................................ 52

Write Buffer Programming ......................................................................... 52

Accelerated Program .....................................................................................53

Figure 1. Write Buffer Programming Operation....................... 54

Figure 2. Program Operation ............................................... 55

Input/Output Descriptions . . . . . . . . . . . . . . . . . . . 11

Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 12

Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . 16

S29GLxxxN MirrorBit

Flash Family

Datasheet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

General Description . . . . . . . . . . . . . . . . . . . . . . . 20

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Device Bus Operations . . . . . . . . . . . . . . . . . . . . . . 23

Table 1. Device Bus Operations ........................................... 23

Program Suspend/Program Resume Command Sequence .................... 55

Figure 3. Program Suspend/Program Resume ........................ 56

Chip Erase Command Sequence ................................................................... 56

Sector Erase Command Sequence ................................................................ 57

Figure 4. Erase Operation ................................................... 58

Word/Byte Configuration ................................................................................23

Requirements for Reading Array Data .........................................................23

Page Mode Read ............................................................................................. 24

Writing Commands/Command Sequences ................................................ 24

Write Buffer .................................................................................................... 24

Accelerated Program Operation ...............................................................25

Autoselect Functions .....................................................................................25

Standby Mode .......................................................................................................25

Automatic Sleep Mode ......................................................................................25

RESET#: Hardware Reset Pin .........................................................................25

Output Disable Mode ....................................................................................... 26

Table 2. Sector Address Table–S29GL256N ........................... 26

Table 3. Sector Address Table–S29GL128N ........................... 33

Erase Suspend/Erase Resume Commands .................................................. 58

Lock Register Command Set Definitions .................................................... 59

Password Protection Command Set Definitions ...................................... 59

Non-Volatile Sector Protection Command Set Definitions ................... 61

Global Volatile Sector Protection Freeze Command Set ....................... 61

Volatile Sector Protection Command Set .................................................. 62

Secured Silicon Sector Entry Command ..................................................... 62

Secured Silicon Sector Exit Command ........................................................ 63

Command Definitions ........................................................................................64

Table 10. S29GL512N, S29GL256N, S29GL128N Command

Definitions, x16 .................................................................64

Table 11. S29GL512N, S29GL256N, S29GL128N Command

Definitions, x8 ...................................................................67

Sector Protection ................................................................................................37

Persistent Sector Protection .......................................................................37

Password Sector Protection ........................................................................37

WP# Hardware Protection .........................................................................37

Selecting a Sector Protection Mode .........................................................37

Advanced Sector Protection ...........................................................................38

Lock Register ........................................................................................................38

Table 4. Lock Register ........................................................ 39

Write Operation Status ...................................................................................69

DQ7: Data# Polling ...........................................................................................70

Figure 5. Data# Polling Algorithm ........................................ 71

RY/BY#: Ready/Busy# ........................................................................................ 71

DQ6: Toggle Bit I ............................................................................................... 72

Figure 6. Toggle Bit Algorithm ............................................. 73

Persistent Sector Protection ...........................................................................39

Dynamic Protection Bit (DYB) ...................................................................39

Persistent Protection Bit (PPB) ................................................................. 40

Persistent Protection Bit Lock (PPB Lock Bit) ...................................... 41

Table 5. Sector Protection Schemes ..................................... 41

DQ2: Toggle Bit II ...............................................................................................73

Reading Toggle Bits DQ6/DQ2 ..................................................................... 74

DQ5: Exceeded Timing Limits ........................................................................ 74

DQ3: Sector Erase Timer ................................................................................ 75

DQ1: Write-to-Buffer Abort ........................................................................... 75

Table 12. Write Operation Status .........................................76

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . 76

Figure 7. Maximum Negative Overshoot Waveform................. 77

Figure 8. Maximum Positive

Overshoot Waveform.......................................................... 77

Persistent Protection Mode Lock Bit ........................................................... 41

Password Sector Protection ........................................................................... 42

Password and Password Protection Mode Lock Bit ............................... 42

64-bit Password ...................................................................................................43

Persistent Protection Bit Lock (PPB Lock Bit) ...........................................43

Secured Silicon Sector Flash Memory Region ............................................43

Write Protect (WP#) ........................................................................................45

Hardware Data Protection ..............................................................................45

Low VCC Write Inhibit ................................................................................45

Write Pulse “Glitch” Protection ................................................................45

Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . 77

DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 78

Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Figure 9. Test Setup........................................................... 79

Table 13. Test Specifications ...............................................79

Key to Switching Waveforms . . . . . . . . . . . . . . . . 79

Figure 10. Input Waveforms and Measurement Levels ............ 79

AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 80

S71GL512_256_128NB0_00_A1 December 7, 2004

A d v a n c e

I n f o r m a t i o n

Read-Only Operations–S29GL512N Only ..................................................80

Read-Only Operations–S29GL256N Only .................................................. 81

Read-Only Operations–S29GL128N Only .................................................. 82

Figure 11. Read Operation Timings....................................... 83

Figure 12. Page Read Timings.............................................. 83

Hardware Reset (RESET#) .............................................................................. 84

Figure 13. Reset Timings..................................................... 84

Figure 28. Mode Register .................................................. 122

Figure 29. Mode Register UpdateTimings (UB#, LB#, OE# are Don’t

Care) ............................................................................. 122

Figure 30. Deep Sleep Mode - Entry/Exit Timings (for 64M)... 123

Figure 31. Deep Sleep Mode - Entry/Exit Timings

(for 32M and 16M) ........................................................... 123

Erase and Program Operations–S29GL512N Only .................................. 85

Erase and Program Operations–S29GL256N Only ................................. 86

Erase and Program Operations–S29GL128N Only .................................. 87

Figure 14. Program Operation Timings .................................. 88

Figure 15. Accelerated Program Timing Diagram .................... 88

Figure 16. Chip/Sector Erase Operation Timings..................... 89

Figure 17. Data# Polling Timings

(During Embedded Algorithms) ............................................ 90

Figure 18. Toggle Bit Timings (During Embedded Algorithms) .. 91

Figure 19. DQ2 vs. DQ6 ...................................................... 91

pSRAM Type 7

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . 127

Functional Description . . . . . . . . . . . . . . . . . . . . 128

Power Down ......................................................................................................128

Power Down Program Sequence ................................................................129

Address Key ........................................................................................................129

Alternate CE# Controlled Erase and Program Operations–

S29GL512N Only ................................................................................................ 92

Alternate CE# Controlled Erase and Program Operations–

S29GL256N Only ................................................................................................93

Alternate CE# Controlled Erase and Program Operations–

S29GL128N Only ................................................................................................ 94

Figure 20. Alternate CE# Controlled Write (Erase/Program)

Operation Timings .............................................................. 95

Absolute Maximum Ratings . . . . . . . . . . . . . . . . 130

Package Capacitance . . . . . . . . . . . . . . . . . . . . . 130

Read Operation ................................................................................................. 132

AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . .134

Write Operation ............................................................................................... 134

Power Down Parameters ............................................................................... 135

Other Timing Parameters ............................................................................... 135

AC Test Conditions .........................................................................................136

AC Measurement Output Load Circuit .....................................................136

Figure 32. AC Output Load Circuit ...................................... 136

Latchup Characteristics . . . . . . . . . . . . . . . . . . . . 95

Erase And Programming Performance . . . . . . . 96

TSOP Pin and BGA Package Capacitance . . . . . 96

Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . 137

Read Timings ....................................................................................................... 137

Figure 33. Read Timing #1 (Baisc Timing)........................... 137

Figure 34. Read Timing #2 (OE# Address Access ................. 137

Figure 35. Read Timing #3 (LB#/UB# Byte Access).............. 138

Figure 36. Read Timing #4 (Page Address Access after CE1# Control

Access for 32M and 64M Only)........................................... 138

Figure 37. Read Timing #5 (Random and Page Address Access for

32M and 64M Only).......................................................... 139

pSRAM Type 1

Functional Description . . . . . . . . . . . . . . . . . . . . . 97

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . 97

Timing Test Conditions . . . . . . . . . . . . . . . . . . . 103

Output Load Circuit ........................................................................................104

Figure 21. Output Load Circuit ........................................... 104

Write Timings ....................................................................................................139

Figure 38. Write Timing #1 (Basic Timing) ..........................

Figure 39. Write Timing #2 (WE# Control) ..........................

Figure 40. Write Timing #3-1

(WE#/LB#/UB# Byte Write Control)...................................

Figure 41. Write Timing #3-2

(WE#/LB#/UB# Byte Write Control)...................................

Figure 42. Write Timing #3-3

(WE#/LB#/UB# Byte Write Control)...................................

Figure 43. Write Timing #3-4

(WE#/LB#/UB# Byte Write Control)...................................

Figure 44. Read/Write Timing #1-1 (CE1# Control)..............

Figure 45. Read / Write Timing #1-2

(CE1#/WE#/OE# Control) ................................................

Figure 46. Read / Write Timing #2 (OE#, WE# Control)........

Figure 47. Read / Write Timing #3

(OE#, WE#, LB#, UB# Control).........................................

Figure 48. Power-up Timing #1 .........................................

Figure 49. Power-up Timing #2 .........................................

Figure 50. Power Down Entry and Exit Timing......................

Figure 51. Standby Entry Timing after Read or Write ............

Figure 52. Power Down Program Timing (for 32M/64M Only) .

139

140

141

142

143

144

145

146

Power Up Sequence . . . . . . . . . . . . . . . . . . . . . . 104

AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . 105

Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . 116

Read Cycle ........................................................................................................... 116

Figure 22. Timing of Read Cycle (CE# = OE# = V

, WE# = ZZ# =

)................................................................................ 116

Figure 23. Timing Waveform of Read Cycle

(WE# = ZZ# = V

) ......................................................... 117

Figure 24. Timing Waveform of Page Mode Read Cycle (WE# = ZZ#

= V

) ............................................................................ 118

Figure 25. Timing Waveform of Write Cycle (WE# Control, ZZ# =

)................................................................................ 119

Figure 26. Timing Waveform of Write Cycle (CE# Control, ZZ# =

)................................................................................ 119

Figure 27. Timing Waveform of Page Mode

Write Cycle (ZZ# = V

) ................................................... 120

Read/Write Timings .........................................................................................142

Write Cycle ......................................................................................................... 119

Partial Array Self Refresh (PAR) ...................................................................120

Temperature Compensated Refresh (for 64Mb) ..................................... 121

Deep Sleep Mode ............................................................................................... 121

Reduced Memory Size (for 32M and 16M) .................................................. 121

Other Mode Register Settings (for 64M) .................................................... 121

Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 147

December 7, 2004 S71GL512_256_128NB0_00_A1

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