PUSB3AB4
10
ESD protection for ultra high-speed interfaces
Rev. 1 — 25 August 2015
Objective data sheet
1. Product profile
1.1 General description
The device is designed to protect high-speed interfaces such as SuperSpeed USB 3.1 at
10 Gbps, High-Definition Multimedia Interface (HDMI), DisplayPort, external Serial
Advanced Technology Attachment (eSATA) and Low Voltage Differential Signaling (LVDS)
interfaces against ElectroStatic Discharge (ESD).
The device includes a high-level ESD protection diode structure protecting sensitive
transmitters and receivers for ultra high-speed signal lines. The device is encapsulated in
a leadless small DFN2510A-10 (SOT1176-1) plastic package.
All signal lines are protected by a special diode configuration offering ultra low line
capacitance of only 0.2 pF maximum. These diodes utilize a snapback structure in order
to provide protection to downstream components from ESD voltages up to
15
kV contact
exceeding IEC 61000-4-2, level 4.
XS
ON
1.2 Features and benefits
System-level ESD protection for USB 2.0 and SuperSpeed USB 3.1 at 10 Gbps,
HDMI, DisplayPort, eSATA and LVDS
Line capacitance of only 0.2 pF maximum for each channel
Outstanding system protection: extremely deep snapback combined with dynamic
resistance of only 0.4
.
All signal lines with integrated rail-to-rail clamping diodes for downstream
ESD protection of
15
kV exceeding IEC 61000-4-2, level 4
Matched 0.5 mm trace spacing
Signal lines with
0.05 pF matching capacitance between signal pairs
Design-friendly ‘pass-through’ signal routing
1.3 Applications
The device is designed for high-speed receiver and transmitter port protection:
Smartphones, tablet computers, Mobile Internet Devices (MID) and portable devices
TVs and monitors
DVD recorders and players
Notebooks, main board graphic cards and ports
Set-top boxes and game consoles
NXP Semiconductors
PUSB3AB4
ESD protection for ultra high-speed interfaces
2. Pinning information
Table 1.
Pin
1
2
3
4
5
6
7
8
9
10
CH1
CH2
GND
CH3
CH4
n.c.
n.c.
GND
n.c.
n.c.
Pinning
Description
channel 1 ESD protection
channel 2 ESD protection
ground
channel 3 ESD protection
channel 4 ESD protection
not connected
not connected
ground
not connected
not connected
aaa-019396
Symbol
Simplified outline
10
9
8
7
6
Graphic symbol
1
2
4
5
1
2
3
4
5
Transparent top view
3,8
=
3. Ordering information
Table 2.
Ordering information
Package
Name
PUSB3AB4
DFN2510A-10
Description
Version
plastic extremely thin small outline package;
SOT1176-1
no leads; 10 terminals; body 1
2.5
0.5 mm
Type number
4. Marking
Table 3.
Marking codes
Marking code
AB
Type number
PUSB3AB4
5. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
V
I
V
ESD
Parameter
input voltage
electrostatic discharge
voltage
IEC 61000-4-2, level 4
contact discharge
air discharge
I
PPM
T
amb
T
stg
[1]
PUSB3AB4
Conditions
[1]
Min
0.5
15
15
7
40
55
Max
+3.3
+15
+15
7
+85
+125
Unit
V
kV
kV
A
C
C
rated peak pulse current
ambient temperature
storage temperature
t
p
= 8/20
s
All pins to ground.
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Objective data sheet
Rev. 1 — 25 August 2015
2 of 9
NXP Semiconductors
PUSB3AB4
ESD protection for ultra high-speed interfaces
6. Characteristics
Table 5.
Characteristics
T
amb
= 25
C unless otherwise specified.
Symbol
V
BR
I
LR
V
F
C
line
r
dyn
Parameter
breakdown voltage
forward voltage
line capacitance
dynamic resistance
TLP
positive transient
negative transient
V
sbck
V
CL
snapback voltage
clamping voltage
I
I
= 1 A; TLP 100/10 ns
I
PP
= 5 A; positive transient
I
PP
=
5
A;
negative transient
[1]
[2]
[3]
This parameter is guaranteed by design.
100 ns Transmission Line Pulse (TLP); 50
;
pulser at 80 ns.
According to IEC 61000-4-5 (8/20
s
current waveform).
[3]
[3]
Conditions
I
I
= 1 mA
I
I
= 1 mA
[1]
[2]
Min
5.5
-
-
-
-
-
-
-
-
Typ
9
<1
0.7
0.17
0.4
0.4
3.3
4.5
4.5
Max
-
100
-
0.2
-
-
-
-
-
Unit
V
nA
V
pF
V
V
V
reverse leakage current per channel; V
I
= 5 V
The device uses an advanced clamping structure showing a negative dynamic resistance.
This snapback behavior strongly reduces the clamping voltage to the system behind the
ESD protection during an ESD event. Do not connect unlimited DC current sources to the
data lines to avoid keeping the ESD protection device in snap-back state after exceeding
breakdown voltage (due to an ESD pulse for instance).
7. Application information
The device is designed to provide high-level ESD protection for high-speed serial
data buses such as HDMI, DisplayPort, eSATA and LVDS data lines.
When designing the PCB, give careful consideration to impedance matching and signal
coupling. Do not connect the signal lines to unlimited current sources like, for example, a
battery.
PUSB3AB4
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Objective data sheet
Rev. 1 — 25 August 2015
3 of 9
NXP Semiconductors
PUSB3AB4
ESD protection for ultra high-speed interfaces
8. Package outline
1.1
0.9
0.2 min
5
6
0.127
2.6
2
2.4
0.25
0.15
0.5
1
10
0.4
0.3
0.05 max
0.5 max
12-05-23
0.45
0.35
Dimensions in mm
Fig 1.
Package outline DFN2510A-10 (SOT1176-1)
PUSB3AB4
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Objective data sheet
Rev. 1 — 25 August 2015
4 of 9
NXP Semiconductors
PUSB3AB4
ESD protection for ultra high-speed interfaces
9. Soldering
Footprint information for reflow soldering of DFN2510A-10 package
SOT1176-1
Hx
C
Hy
Ay
By
0.05
D
P
0.05
Generic footprint pattern
Refer to the package outline drawing for actual layout
solder land
solder paste deposit
solder land plus solder paste
occupied area
solder resist
Dimensions in mm
P
0.5
Ay
1.25
By
0.3
C
0.475
D
0.2
Hx
2.45
Hy
1.5
Remark:
Stencil of 75
μ
m is recommended.
A stencil of 75
μ
m gives an aspect ratio of 0.77
With a stencil of 100
μ
m one will obtain an aspect ratio of 0.58
sot1176-1_fr
Fig 2.
Reflow soldering footprint DFN2510A-10 (SOT1176-1)
PUSB3AB4
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Objective data sheet
Rev. 1 — 25 August 2015
5 of 9
FPGA/CPLD
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