ST7PL39MC/XXXE datasheet, PDF - EEWORLD Datasheet

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ST7PL39MC/XXXE: Description8-BIT, EEPROM, 8MHz, MICROCONTROLLER, PDSO20, 0.300 INCH, ROHS COMPLIANT, PLASTIC, SOP-20; CategoryThe embedded processor and controller Microcontrollers and processors; File Size2MB，234 Pages; ManufacturerSTMicroelectronics; Websitehttp://www.st.com/; Environmental Compliance

Download Datasheet Parametric View All

ST7PL39MC/XXXE Overview

8-BIT, EEPROM, 8MHz, MICROCONTROLLER, PDSO20, 0.300 INCH, ROHS COMPLIANT, PLASTIC, SOP-20

ST7PL39MC/XXXE Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	STMicroelectronics
Parts packaging code	SOIC
package instruction	0.300 INCH, ROHS COMPLIANT, PLASTIC, SOP-20
Contacts	20
Reach Compliance Code	compliant
Has ADC	YES
Address bus width
bit size	8
CPU series	ST7
maximum clock frequency	16 MHz
DAC channel	NO
DMA channel	NO
External data bus width
JESD-30 code	R-PDSO-G20
length	12.8 mm
Number of I/O lines	15
Number of terminals	20
On-chip program ROM width	8
Maximum operating temperature	125 °C
Minimum operating temperature	-40 °C
PWM channel	YES
Package body material	PLASTIC/EPOXY
encapsulated code	SOP
Encapsulate equivalent code	SOP20,.4
Package shape	RECTANGULAR
Package form	SMALL OUTLINE
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	3.3/5 V
Certification status	Not Qualified
RAM (bytes)	384
rom(word)	8192
ROM programmability	FASTROM
Maximum seat height	2.65 mm
speed	8 MHz
Maximum slew rate	9 mA
Maximum supply voltage	5.5 V
Minimum supply voltage	3 V
Nominal supply voltage	3.3 V
surface mount	YES
technology	CMOS
Temperature level	AUTOMOTIVE
Terminal form	GULL WING
Terminal pitch	1.27 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
width	7.5 mm
uPs/uCs/peripheral integrated circuit type	MICROCONTROLLER

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ST7L34 ST7L35

ST7L38 ST7L39

8-bit MCU for automotive with single voltage Flash/ROM,

data EEPROM, ADC, timers, SPI, LINSCI™

Features

■

Memories

– 8 Kbytes program memory: Single voltage

extended Flash (XFlash) or ROM with

readout protection capability. In-application

programming and in-circuit programming

(IAP and ICP) for XFlash devices

– 384 bytes RAM

– 256 bytes data EEPROM (XFlash and

ROM devices) with readout protection,

300 K write/erase cycles guaranteed

– XFlash and EEPROM data retention

20 years at 55°C

Clock, reset and supply management

– Enhanced reset system

– Enhanced low voltage supervisor (LVD) for

main supply and an auxiliary voltage

detector (AVD) with interrupt capability for

implementing safe power-down procedures

– Clock sources: Internal 1% RC oscillator,

crystal/ceramic resonator or external clock

– Optional x8 PLL for 8 MHz internal clock

– 5 power saving modes: Halt, active halt,

auto wakeup from halt, wait and slow

I/O ports

– Up to 15 multifunctional bidirectional I/O

lines

– 7 high sink outputs

5 timers

– Configurable watchdog timer

– Two 8-bit lite timers with prescaler, 1 real-

time base and 1 input capture

– Two 12-bit autoreload timers with 4 PWM

outputs, 1 input capture and 4 output

compare functions

SO20

300 mil

QFN20

■

2 communication interfaces

– Master/slave LINSCI™ asynchronous

serial interface

– SPI synchronous serial interface

Interrupt management

– 10 interrupt vectors plus TRAP and reset

– 12 external interrupt lines (on 4 vectors)

A/D converter

– 7 input channels

– 10-bit resolution

Instruction set

– 8-bit data manipulation

– 63 basic instructions with illegal opcode

detection

– 17 main addressing modes

– 8 x 8 unsigned multiply instructions

Development tools

– Full hardware/software development

package

– DM (debug module)

■

■

■

■

■

■

■

November 2011

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1

Contents

ST7L34 ST7L35 ST7L38 ST7L39

Contents

1

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

1.1

1.2

Parametric data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Debug module (DM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2

3

4

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Register and memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Flash program memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

4.1

4.2

4.3

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Programming modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

4.3.1

4.3.2

In-circuit programming (ICP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

In-application programming (IAP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

4.4

4.5

ICC interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Memory protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

4.5.1

4.5.2

Readout protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Flash write/erase protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

4.6

4.7

Related documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

5

Data EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

5.1

5.2

5.3

5.4

5.5

5.6

5.7

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Memory access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Access error handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Data EEPROM readout protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

6

Central processing unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

6.1

6.2

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

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Contents

6.3

CPU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

7

Supply, reset and clock management . . . . . . . . . . . . . . . . . . . . . . . . . . 37

7.1

7.2

7.3

7.4

Internal RC oscillator adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Phase locked loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Multi-oscillator (MO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

7.4.1

7.4.2

7.4.3

External clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Crystal/ceramic oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Internal RC oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

7.5

Reset sequence manager (RSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

7.5.1

7.5.2

7.5.3

7.5.4

7.5.5

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Asynchronous external RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

External power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Internal low voltage detector (LVD) reset . . . . . . . . . . . . . . . . . . . . . . . . 44

Internal watchdog reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

7.6

System integrity management (SI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

7.6.1

7.6.2

7.6.3

7.6.4

Low voltage detector (LVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

8

Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

8.1

8.2

8.3

Non maskable software interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

External interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Peripheral interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

9

Power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

9.1

9.2

9.3

9.4

9.5

9.6

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Slow mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

9.4.1

Halt mode recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Active halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Auto wakeup from halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

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ST7L34 ST7L35 ST7L38 ST7L39

10

I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

10.1

10.2

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

10.2.1

10.2.2

10.2.3

Input modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Output modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

10.3

10.4

10.5

10.6

10.7

I/O port implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Unused I/O pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Device-specific I/O port configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

11

On-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

11.1

Watchdog timer (WDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

11.1.1

11.1.2

11.1.3

11.1.4

11.1.5

11.1.6

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Hardware watchdog option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

11.2

Dual 12-bit autoreload timer 3 (AT3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

11.2.1

11.2.2

11.2.3

11.2.4

11.2.5

11.2.6

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

11.3

Lite timer 2 (LT2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

11.3.1

11.3.2

11.3.3

11.3.4

11.3.5

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

11.4

Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

11.4.1

11.4.2

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

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ST7L34 ST7L35 ST7L38 ST7L39

11.4.3

11.4.4

11.4.5

11.4.6

11.4.7

11.4.8

Contents

General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

Clock phase and clock polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

Error flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

11.5

LINSCI serial communication interface (LIN master/slave) . . . . . . . . . . 122

11.5.1

11.5.2

11.5.3

11.5.4

11.5.5

11.5.6

11.5.7

11.5.8

11.5.9

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

SCI features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

LIN features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

SCI mode - functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

SCI mode registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

LIN mode - functional description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

11.5.10 LIN mode register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

11.6

10-bit A/D converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

11.6.1

11.6.2

11.6.3

11.6.4

11.6.5

11.6.6

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165

Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165

Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166

12

Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169

12.1

ST7 addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169

12.1.1

12.1.2

12.1.3

12.1.4

12.1.5

12.1.6

12.1.7

Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171

Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171

Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172

Indexed (no offset, short, long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172

Indirect (short, long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172

Indirect indexed (short, long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173

Relative mode (direct, indirect) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174

12.2

Instruction groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174

12.2.1

12.2.2

Using a prebyte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

Illegal opcode reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

Doc ID 11928 Rev 8

5/234

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