IMP5121
D
ATA
C
OMMUNICATIONS
27-Line Plug and Play
SCSI Terminator
The 27-channel IMP5121 SCSI terminator is part of IMP's family of high-
performance SCSI terminators that deliver true UltraSCSI performance.
The BiCMOS design offers superior performance over first generation
linear regulator/resistor based terminators.
IMP's new architecture employs high-speed adaptive elements for each
channel, thereby providing the fastest response possible - typically
35MHz, which is 100 times faster than the older linear regulator termi-
nator approach. The bandwidth of terminators based on the older
regulator/resistor terminator architecture is limited to 500kHz since a
large output stabilization capacitor is required. The IMP architecture
eliminates the external output compensation capacitor and the need
for transient output capacitors while maintaining pin compatibility
with first generation designs. Reduced component count is inherent
with the IMP5121.
The IMP5121 architecture tolerates marginal system designs. A key
improvement offered by the IMP5121 lies in its ability to insure reliable,
error-free communications even in systems which do not adhere to rec-
ommended SCSI hardware design guidelines, such as improper cable
lengths and impedance. Frequently, this situation is not controlled by the
peripheral or host designer.
For portable and configurable peripherals, the IMP5121 can be placed in
a sleep mode with TTL compatible signals. Quiescent current is less than
150µA when disabled.
Key Features
x
SCSI Plug and Play
— Host bus adapter with 3 SCSI connectors
x
Ultra-Fast response for Fast-20 SCSI
x
Split disconnect for mixing 16-bit (wide) or
8-bit (narrow) buses
x
35MHz channel bandwidth
x
Sleep-mode current less than 150µA
x
NO external compensation capacitors
x
Compatible with active negation drivers
x
Hot swap compatible
x
Superior replacement for the LX5121 and
UCC5621
For Host Bus Adapters and three SCSI connectors, the
IMP5121 has multiple disable pins for Plug and Play SCSI
capability. It also splits the upper nine termination lines for
mixing 16-bit (wide) and 8-bit (narrow) buses with minimal
board trace capacitance.
Block Diagrams
Term Power
V
TERM
Current
Biasing
Circuit
24mA Current
Limiting Circuit
DATA OUTPUT
PIN DB (0)
2.85V
DISCONNECT 1
DISCONNECT 2
Enable
Logic
–
1 of 27 Channels
+
1.4V
V
TERM
5121_01.eps
© 2002 IMP, Inc.
408-432-9100/www.impweb.com
1
IMP5121
Pin Configuration
SSOP-44
T19
T20
T1
T2
W1
W2
T3
T4
T5
1
2
3
4
5
6
7
8
9
IMP5121
44 T27
43 T26
42 T25
41 T18
40 N1
39 T17
38 T16
37 T15
36 NC
35 GND
34 GND
33 GND
32 GND
31 V
1
30 T14
29 T13
28 T12
27 NC
26 NC
25 T11
24 T24
23 T23
5121_02.eps
TSSOP-56
T19
T20
T1
T2
W1
W2
T3
T4
T5
1
2
3
4
5
6
7
8
9
56 T27
55 T26
54 T25
53 T18
52 N1
51 T17
50 T16
49 T15
48 NC
47 GND
46 GND
45 HEAT SINK
44 HEAT SINK
IMP5121
43 HEAT SINK
42 HEAT SINK
41 HEAT SINK
40 HEAT SINK
39 GND
38 GND
37 V
1
36 T14
35 T13
34 T12
33 NC
32 NC
31 T11
30 T24
29 T23
5121_02a.eps
GND 10
GND 11
GND 12
GND 13
DISCONNECT 1 14
DISCONNECT 2 15
T6 16
T7 17
T8 18
T9 19
T10 20
T21 21
T22 22
GND 10
GND 11
HEAT SINK 12
HEAT SINK 13
HEAT SINK 14
HEAT SINK 15
HEAT SINK 16
HEAT SINK 17
GND 18
GND 19
DISCONNECT 1 20
DISCONNECT 2 21
T6 22
T7 23
T8 24
T9 25
T10 26
T21 27
T22 28
PW Package
DB Package
Ordering Information
Part Number
IMP5121CDB
IMP5121CPW
Temperature Range
0°C to 125°C
0°C to 125°C
Package
44-pin Plastic SSOP
56-pin Plastic TSSOP
5121_t01.at3
Absolute Maximum Ratings
1
TermPwr Voltage . . . . . . . . . . . . . . . . . . . . . . . . +7V
Continuous Output Voltage Range . . . . . . . . 0V to 5.5V
Continuous Disable Voltage Range . . . . . . . . 0V to 5.5V
Operating Junction Temperature . . . . . . . . . . 150°C
Storage Temperature Range . . . . . . . . . . . . . . –65°C to 150°C
Lead Temperature (Soldering, 10 sec.) . . . . . . 300°C
Note: 1. Exceeding these ratings could cause damage to the device. All
voltages are with respect to Ground. Currents are positive
into, negative out of the specified terminal.
Thermal Data
PW and DB Package
Thermal Resistance Junction-to-Ambient,
θ
JA
. . . . . . 50°C/W
Junction Temperature Calculation: T
J
= T
A
+ (P
D
x
θ
JA
).
The
θ
JA
numbers are guidelines for the thermal performance of the
device/pc-board system. All of the ambient airflow is assumed.
2
408-432-9100/www.impweb.com
© 2002 IMP, Inc.
IMP5121
Recommended Operating Conditions
Parameter
Termpwr Voltage
High Level Disable Input Voltage
Low Level Disable Input Voltage
Operating Junction Temperature Range – IMP5121C
Symbol
V
TERM
V
IH
V
IL
Min
4.0
2
0
0
Typ
Max
5.5
V
TERM
0.8
125
Units
V
V
V
°C
5225_t02.eps
Note:
2. Recommended operating conditions indicate the range over which the device is functional.
Electrical Characteristics
Unless otherwise specified, these specifications apply at an ambient operating temperature of T
A
=
25°C. TermPwr = 4.75V. Low duty cycle
pulse testing techniques are used which maintains junction and case temperatures equal to the ambient temperature.
Parameter
Output High Voltage
TermPwr Supply Current
Symbol Conditions
V
OUT
I
CC
All data lines = Open
All data lines = 0.5V
Disable Pins 1, 2 < 0.8V
Min
2.65
Typ
2.85
12
635
50
Max
20
670
150
–24
–10
1
Units
V
mA
µA
mA
µA
µA
MHz
mA
5121_t03.eps
Output Current
Disconnect Input Current
Output Leakage Current
Channel Bandwidth
Termination Sink Current, per Channel
I
OUT
I
IN
I
OL
BW
I
SINK
V
OUT
= 0.5V
DISCONNECT Pins = 0V
DISCONNECT Pins < 0.8V, V
O
= 0.2V
–20
–22
35
V
OUT
= 4V
7
© 2002 IMP, Inc.
Data Communications
3
IMP5121
Application Information
Figure 1. Receiving Waveform – 20MHz
Figure 2. Driving Waveform – 20MHz
Receiver
1 Meter, AWG 28
IMP5121
Driver
IMP5121
5121_03.eps
Figure 3.
IMP5121 Maximizes Line Current
Cable transmission theory suggests to optimize signal speed and
quality, the termination should act both as an ideal voltage refer-
ence when the line is released (deasserted) and as an ideal
current source when the line is active (asserted). Common active
terminators which consist of linear regulators in series with resis-
tors (typically 110Ω) are a compromise. With coventional linear
terminators as the line voltage increases the amount of current
decreases linearly by the equation;
Acting as a near ideal line terminator, the IMP5121 closely repro-
duces the optimum case when the device is enabled. To enable
the device the DISC1 and DISC2 pins must be driven per
Table 1.
When enabled, quiescent current is 12mA and the device will
respond to line demands by delivering 24mA on assertion and by
imposing 2.85V on de-assertion.
Disable/Sleep Mode
Disable mode places the device in a sleep state, where quiescent
current is reduced to less than 150µA. When disabled, all
outputs are in a high impedance state. Sleep mode can be used
for power conservation or to remove the terminator from the
SCSI chain.
An additional feature of the IMP5121 is its compatibility with
active negation drivers.
(
V
REF
−
V
LINE
)
=
I.
R
The IMP5121, with its unique new architecture, applies the max-
imum amount of current regardless of line voltage until the
termination high threshold (2.85V) is reached.
4
408-432-9100/www.impweb.com
© 2002 IMP, Inc.
IMP5121
Application Information
Table 1. Power Up/ Power Down Function Table
DISCONNECT 1
H
L
L
H
H
H
H
H
H
H
H
DISCONNECT 2
L
H
L
H
H
H
H
H
H
H
H
W1
DC
DC
DC
H
H
H
H
L
L
L
L
W2
DC
DC
DC
H
H
L
L
H
H
L
L
N1
DC
DC
DC
H
L
H
L
H
L
H
L
T1-T18
Enabled
Disabled
Disabled
Enabled
Enabled
Enabled
Disabled
Enabled
Disabled
Disabled
Disabled
T19-T27
Disabled
Enabled
Disabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Disabled
Disabled
5121_t04.eps
For Plug and Play SCSI auto-termination
disabling, connect pin 50 of the External Wide
SCSI connector to W1 of the IMP5121,
connect pin 50 of the Internal Wide SCSI
connector to W2 of the IMP5121, and connect
pin 22 of the Internal Narrow connector to N1
of the IMP5121.
Internal Narrow
Internal Wide
External
Wide
IMP5121
5121_05.eps
Figure 4. Plug and Play Diagram
© 2002 IMP, Inc.
Data Communications
5
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