5P49V6975A000LTGI8 datasheet, PDF

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5P49V6975A000LTGI8: DescriptionLGA-24, Reel; CategoryThe embedded processor and controller Microcontrollers and processors; File Size1MB，31 Pages; ManufacturerIDT (Integrated Device Technology); Environmental Compliance

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5P49V6975A000LTGI8 Overview

LGA-24, Reel

5P49V6975A000LTGI8 Parametric

Parameter Name	Attribute value
Brand Name	Integrated Device Technology
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	IDT (Integrated Device Technology)
Parts packaging code	LGA
package instruction	HLGA,
Contacts	24
Manufacturer packaging code	LTG24T2
Reach Compliance Code	compliant
Samacsys Description	LGA 4MM X 4MM
Other features	ALSO OPERATES AT 2.5V AND 3.3V NOMINAL SUPPLY
JESD-30 code	S-PBGA-B24
JESD-609 code	e3
length	4 mm
Humidity sensitivity level	3
Number of terminals	24
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Maximum output clock frequency	350 MHz
Package body material	PLASTIC/EPOXY
encapsulated code	HLGA
Package shape	SQUARE
Package form	GRID ARRAY, HEAT SINK/SLUG
Peak Reflow Temperature (Celsius)	260
Master clock/crystal nominal frequency	350 MHz
Maximum seat height	1.49 mm
Maximum supply voltage	3.465 V
Minimum supply voltage	1.71 V
Nominal supply voltage	1.8 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Tin (Sn)
Terminal form	BUTT
Terminal pitch	0.5 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED
width	4 mm
uPs/uCs/peripheral integrated circuit type	CLOCK GENERATOR, PROCESSOR SPECIFIC

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VersaClock

6E Programmable

Clock with Internal Crystal

Description

The 5P49V6975 is a programmable clock generator intended for

high-performance consumer, networking, industrial, computing,

and data-communications applications. The device is a member of

Renesas’ sixth generation of programmable clock technology,

VersaClock 6E.

The 5P49V6975 contains an internal crystal, which eliminates the

need for external crystal and load cap tuning.

Two select pins allow up to four different configurations to be

programmed, and can be used for different operating modes (full

function, partial function, partial power-down), regional standards

(US, Japan, Europe) or system production margin testing. The

5P49V6975 can be configured to use one of two I

C addresses to

allow the use of multiple devices in a system.

5P49V6975

Datasheet

Features



Typical Applications



Ethernet switch/router

PCI Express 1.0/2.0/3.0/4.0 spread spectrum on

PCI Express 1.0/2.0/3.0/4.0/5.0 spread spectrum off

Broadcast video/audio timing

Multi-function printer

Processor and FPGA clocking

Any-frequency clock conversion

MSAN/DSLAM/PON

Fiber Channel, SAN

Telecom line cards

Laser distance sensing



Internal crystal input integrated into package

Flexible 1.8V, 2.5V, 3.3V power rails

High-performance, low phase noise PLL, < 0.5ps RMS typical

phase jitter on outputs

Four banks of internal OTP memory

• In-system or factory programmable

• Two select pins accessible with processor GPIOs or

bootstrapping

C serial programming interface

• 0xD0 or 0xD4 I

C address options allow multiple devices

configured in a same system

Reference LVCMOS output clock

Four universal output pairs individually configurable:

• Differential (LVPECL, LVDS, or HCSL)

• Two single-ended (2 LVCMOS in-phase or 180 degrees out

of phase)

• I/O VDDs can be mixed and matched, supporting 1.8V

(LVDS and LVCMOS), 2.5V, or 3.3V

• Independent spread spectrum on each output pair

Output frequency ranges:

• LVCMOS clock outputs: 1kHz to 200MHz

• LVDS, LVPECL, HCSL differential clock outputs: 1kHz to

350MHz

Programmable output enable or power-down mode

Available in 4 × 4 mm 24-LGA package

-40° to +85°C industrial temperature operation

Block Diagram

DDO

OUT0_SEL_I2CB

DDO

CLKIN

CLKINB

CLKSEL

SD/OE

SEL1/SDA

SEL0/SCL

DDA

DDD

OTP

and

Control

Logic

FOD2

PLL

OUT1

FOD1

OUT1B

DDO

OUT2

OUT2B

DDO

FOD3

OUT3

OUT3B

DDO

FOD4

OUT4

OUT4B

February 11, 2021

5P49V6975 Datasheet

Contents

Pin Assignments ...........................................................................................................................................................................................3

Pin Descriptions............................................................................................................................................................................................3

Absolute Maximum Ratings ..........................................................................................................................................................................5

Thermal Characteristics................................................................................................................................................................................5

Recommended Operating Conditions...........................................................................................................................................................5

Electrical Characteristics ..............................................................................................................................................................................6

Test Loads ..................................................................................................................................................................................................13

Jitter Performance Characteristics..............................................................................................................................................................14

PCI Express Jitter Performance and Specification .....................................................................................................................................15

10.1 Device Startup and Power-on-Reset................................................................................................................................................17

10.2 Reference Clock and Selection ........................................................................................................................................................18

10.3 Manual Switchover...........................................................................................................................................................................18

10.4 Programmable Loop Filter................................................................................................................................................................19

10.5 Fractional Output Dividers (FOD).....................................................................................................................................................19

10.5.1

10.5.2

10.5.3

10.5.4

10.5.5

Individual Spread Spectrum Modulation ...........................................................................................................................19

Bypass Mode ....................................................................................................................................................................19

Cascaded Mode ................................................................................................................................................................19

Dividers Alignment ............................................................................................................................................................19

Programmable Skew.........................................................................................................................................................20

10. Features and Functional Blocks .................................................................................................................................................................17

10.6 Output Drivers ..................................................................................................................................................................................20

10.7 SD/OE Pin Function .........................................................................................................................................................................20

10.8 I

C Operation ...................................................................................................................................................................................21

11. Typical Application Circuit ..........................................................................................................................................................................22

11.1 Input – Driving the CLKIN ................................................................................................................................................................23

11.1.1

11.1.2

11.2.1

11.2.2

11.2.3

11.2.4

Wiring the CLKIN Pin to Accept Single-Ended Inputs .......................................................................................................23

Driving CLKIN with Differential Clock ................................................................................................................................24

LVDS Termination.............................................................................................................................................................24

LVPECL Termination ........................................................................................................................................................25

HCSL Termination.............................................................................................................................................................26

LVCMOS Termination .......................................................................................................................................................26

11.2 Output – Single-ended or Differential Clock Terminations ...............................................................................................................24

12. Package Outline Drawings .........................................................................................................................................................................26

13. Marking Diagram .........................................................................................................................................................................................27

14. Ordering Information ...................................................................................................................................................................................27

15. Revision History ..........................................................................................................................................................................................28

February 11, 2021

5P49V6975A000LTGI8 Related Products

	5P49V6975A000LTGI8	5P49V6975A000LTGI
Description	LGA-24, Reel	LGA-24, Tray
Brand Name	Integrated Device Technology	Integrated Device Technology
Is it lead-free?	Lead free	Lead free
Is it Rohs certified?	conform to	conform to
Maker	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)
Parts packaging code	LGA	LGA
package instruction	HLGA,	HLGA,
Contacts	24	24
Manufacturer packaging code	LTG24T2	LTG24T2
Reach Compliance Code	compliant	compliant
Samacsys Description	LGA 4MM X 4MM	LGA 4MM X 4MM
Other features	ALSO OPERATES AT 2.5V AND 3.3V NOMINAL SUPPLY	ALSO OPERATES AT 2.5V AND 3.3V NOMINAL SUPPLY
JESD-30 code	S-PBGA-B24	S-PBGA-B24
JESD-609 code	e3	e3
length	4 mm	4 mm
Humidity sensitivity level	3	3
Number of terminals	24	24
Maximum operating temperature	85 °C	85 °C
Minimum operating temperature	-40 °C	-40 °C
Maximum output clock frequency	350 MHz	350 MHz
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	HLGA	HLGA
Package shape	SQUARE	SQUARE
Package form	GRID ARRAY, HEAT SINK/SLUG	GRID ARRAY, HEAT SINK/SLUG
Peak Reflow Temperature (Celsius)	260	260
Master clock/crystal nominal frequency	350 MHz	350 MHz
Maximum seat height	1.49 mm	1.49 mm
Maximum supply voltage	3.465 V	3.465 V
Minimum supply voltage	1.71 V	1.71 V
Nominal supply voltage	1.8 V	1.8 V
surface mount	YES	YES
technology	CMOS	CMOS
Temperature level	INDUSTRIAL	INDUSTRIAL
Terminal surface	Tin (Sn)	Tin (Sn)
Terminal form	BUTT	BUTT
Terminal pitch	0.5 mm	0.5 mm
Terminal location	BOTTOM	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED	NOT SPECIFIED
width	4 mm	4 mm
uPs/uCs/peripheral integrated circuit type	CLOCK GENERATOR, PROCESSOR SPECIFIC	CLOCK GENERATOR, PROCESSOR SPECIFIC

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