GS8162ZV36BGD-150 datasheet, PDF

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GS8162ZV36BGD-150: DescriptionZBT SRAM, 512KX36, 7.5ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, FBGA-165; Categorystorage storage; File Size889KB，31 Pages; ManufacturerGSI Technology; Websitehttp://www.gsitechnology.com/; Environmental Compliance

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GS8162ZV36BGD-150 Overview

ZBT SRAM, 512KX36, 7.5ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, FBGA-165

GS8162ZV36BGD-150 Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	GSI Technology
Parts packaging code	BGA
package instruction	LBGA,
Contacts	165
Reach Compliance Code	compliant
ECCN code	3A991.B.2.B
Maximum access time	7.5 ns
Other features	FLOW-THROUGH OR PIPELINED ARCHITECTURE
JESD-30 code	R-PBGA-B165
JESD-609 code	e1
length	15 mm
memory density	18874368 bit
Memory IC Type	ZBT SRAM
memory width	36
Humidity sensitivity level	3
Number of functions	1
Number of terminals	165
word count	524288 words
character code	512000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	512KX36
Package body material	PLASTIC/EPOXY
encapsulated code	LBGA
Package shape	RECTANGULAR
Package form	GRID ARRAY, LOW PROFILE
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	260
Certification status	Not Qualified
Maximum seat height	1.4 mm
Maximum supply voltage (Vsup)	2 V
Minimum supply voltage (Vsup)	1.6 V
Nominal supply voltage (Vsup)	1.8 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Silver/Copper (Sn/Ag/Cu)
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED
width	13 mm

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Preliminary

GS8162ZV18/36B(B/D)

119- & 165-Bump BGA

Commercial Temp

Industrial Temp

Features

• NBT (No Bus Turn Around) functionality allows zero wait

Read-Write-Read bus utilization; fully pin-compatible with

both pipelined and flow through NtRAM™, NoBL™ and

ZBT™ SRAMs

• 1.8 V +10%/–10% core power supply

• 1.8 V I/O supply

• User-configurable Pipeline and Flow Through mode

• ZQ mode pin for user-selectable high/low output drive

• IEEE 1149.1 JTAG-compatible Boundary Scan

• On-chip write parity checking; even or odd selectable

• On-chip parity encoding and error detection

• LBO pin for Linear or Interleave Burst mode

• Pin-compatible with 2M, 4M, and 8M devices

• Byte write operation (9-bit Bytes)

• 3 chip enable signals for easy depth expansion

• ZZ Pin for automatic power-down

• JEDEC-standard 119-, 165-, or 209-Bump BGA package

18Mb Pipelined and Flow Through

Synchronous NBT SRAM

250 MHz–150 MHz

1.8 V V

1.8 V I/O

Because it is a synchronous device, address, data inputs, and

read/write control inputs are captured on the rising edge of the

input clock. Burst order control (LBO) must be tied to a power

rail for proper operation. Asynchronous inputs include the

Sleep mode enable (ZZ) and Output Enable. Output Enable can

be used to override the synchronous control of the output

drivers and turn the RAM's output drivers off at any time.

Write cycles are internally self-timed and initiated by the rising

edge of the clock input. This feature eliminates complex off-

chip write pulse generation required by asynchronous SRAMs

and simplifies input signal timing.

The GS8162ZV18/36B(B/D) may be configured by the user to

operate in Pipeline or Flow Through mode. Operating as a

pipelined synchronous device, in addition to the rising-edge-

triggered registers that capture input signals, the device

incorporates a rising edge triggered output register. For read

cycles, pipelined SRAM output data is temporarily stored by

the edge-triggered output register during the access cycle and

then released to the output drivers at the next rising edge of

clock.

The GS8162ZV18/36B(B/D) is implemented with GSI's high

performance CMOS technology and is available in a JEDEC-

standard 119-bump or 165-bump BGA package.

Functional Description

The GS8162ZV18/36B(B/D) is an 18Mbit Synchronous Static

SRAM. GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or

other pipelined read/double late write or flow through read/

single late write SRAMs, allow utilization of all available bus

bandwidth by eliminating the need to insert deselect cycles

when the device is switched from read to write cycles.

Parameter Synopsis

-250

Pipeline

3-1-1-1

tCycle

Curr (x18)

Curr (x32/x36)

tCycle

Curr (x18)

Curr (x32/x36)

2.5

4.0

280

330

5.5

210

240

-200

3.0

5.0

230

270

6.5

185

205

-150

3.8

6.7

185

210

7.5

170

190

Unit

Flow Through

2-1-1-1

Rev: 1.00 9/2004

1/31

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

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