V58C2512164SALF5I datasheet, PDF

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V58C2512164SALF5I: DescriptionDDR DRAM, 32MX16, 0.65ns, CMOS, PBGA60, ROHS COMPLIANT, MO-207, FBGA-60; Categorystorage storage; File Size914KB，60 Pages; ManufacturerProMOS Technologies Inc; Environmental Compliance

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V58C2512164SALF5I Overview

DDR DRAM, 32MX16, 0.65ns, CMOS, PBGA60, ROHS COMPLIANT, MO-207, FBGA-60

V58C2512164SALF5I Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	ProMOS Technologies Inc
Parts packaging code	DSBGA
package instruction	TBGA,
Contacts	60
Reach Compliance Code	compliant
ECCN code	EAR99
access mode	FOUR BANK PAGE BURST
Maximum access time	0.65 ns
Other features	AUTO/SELF REFRESH
JESD-30 code	R-PBGA-B60
length	12 mm
memory density	536870912 bit
Memory IC Type	DDR DRAM
memory width	16
Number of functions	1
Number of ports	1
Number of terminals	60
word count	33554432 words
character code	32000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	32MX16
Package body material	PLASTIC/EPOXY
encapsulated code	TBGA
Package shape	RECTANGULAR
Package form	GRID ARRAY, THIN PROFILE
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
Certification status	Not Qualified
Maximum seat height	1.2 mm
self refresh	YES
Maximum supply voltage (Vsup)	2.7 V
Minimum supply voltage (Vsup)	2.5 V
Nominal supply voltage (Vsup)	2.6 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED
width	10 mm

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V58C2512(804/404/164)SA*I

HIGH PERFORMANCE 512 Mbit DDR SDRAM

4 BANKS X 16Mbit X 8 (804)

4 BANKS X 32Mbit X 4 (404)

4 BANKS X 8Mbit X 16 (164)

DDR400

Clock Cycle Time (t

CK2

)

Clock Cycle Time (t

CK2.5

)

Clock Cycle Time (t

CK3

)

System Frequency (f

CK max

)

7.5 ns

6ns

5ns

200 MHz

DDR333

7.5 ns

6 ns

166 MHz

Features

■

High speed data transfer rates with system frequency

up to 200MHz

■

Data Mask for Write Control

■

Four Banks controlled by BA0 & BA1

■

Programmable CAS Latency: 2, 2.5, 3

■

Programmable Wrap Sequence: Sequential

or Interleave

■

Programmable Burst Length:

2, 4, 8 for Sequential Type

2, 4, 8 for Interleave Type

■

Automatic and Controlled Precharge Command

■

Power Down Mode

■

Auto Refresh and Self Refresh

■

Refresh Interval: 8096 cycles/64 ms

■

Available in 60 Ball FBGA AND 66 Pin TSOP II

■

SSTL-2 Compatible I/Os

■

Double Data Rate (DDR)

■

Bidirectional Data Strobe (DQS) for input and output

data, active on both edges

■

On-Chip DLL aligns DQ and DQs transitions with CK

transitions

■

Differential clock inputs CK and CK

■

Power Supply 2.5V ± 0.2V

■

Power Supply 2.6V ± 0.1V for DDR400

■

tRAS lockout supported

■

Concurrent auto precharge option is supported

■

Industrial Temp (TA): -40C to +85C

*Note:

(-5) Supports PC3200 module with 3-3-3 timing

(-6) Supports PC2700 module with 2.5-3-3 timing

Description

The V58C2512(804/404/164)SA*I is a four bank DDR

DRAM organized as 4 banks x 16Mbit x 8 (804), 4 banks x

32Mbit x 4 (404), 4 banks x 8Mbit x 16 (164). The

V58C2512(804/404/164)SA*I achieves high speed data

transfer rates by employing a chip architecture that

prefetches multiple bits and then synchronizes the output

data to a system clock.

All of the control, address, circuits are synchronized

with the positive edge of an externally supplied clock. I/O

transactions are occurring on both edges of DQS.

Operating the four memory banks in an interleaved

fashion allows random access operation to occur at a

higher rate than is possible with standard DRAMs. A se-

quential and gapless data rate is possible depending on

burst length, CAS latency and speed grade of the device.

Device Usage Chart

Operating

Temperature

Range

-40°C to +85°C

V58C2512(804/404/164)SA*I Rev.1.6 May 2007

Package Outline

JEDEC 66 TSOP II

60 FBGA

•

CK Cycle Time (ns)

-5

•

Power

Std.

•

-6

•

Temperature

Mark

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