UTRON
Preliminary Rev. 0.1
64K X 16 BIT LOW POWER CMOS SRAM
GENERAL DESCRIPTION
The UT62L6416 is a 1,048,576-bit low power
CMOS static random access memory organized
as 65,536 words by 16 bits.
The UT62L6416 operates from a single 2.7V ~
3.6V power supply and all inputs and outputs are
fully TTL compatible.
The UT62L6416 is design for upper and low byte
access by data byte control( UB
LB
).
UT62L6416
FEATURES
Fast access time :
55ns(max) for Vcc=3.0V~3.6V
70/100ns(max) for Vcc=2.7V~3.6V
CMOS Low operating power
Operating current: 45/35/25mA (Icc max)
Standby current: 20 uA(TYP.) L-version
3 uA(TYP.) LL-version
Single 2.7V~3.6V power supply
Operating temperature:
Commercial : 0
℃
~70
℃
Extended : -20
℃
~80
℃
All inputs and outputs TTL compatible
Fully static operation
Three state outputs
Data retention voltage: 1.5V (min)
Data byte control :
LB
(I/O1~I/O8)
UB (I/O9~I/O16)
Package : 44-pin 400mil TSOP
Ⅱ
48-pin 6mm × 8mm TFBGA
PIN DESCRIPTION
SYMBOL
A0 - A15
I/O1 - I/O16
CE
WE
OE
LB
UB
V
CC
V
SS
NC
VCC
VSS
DESCRIPTION
Address Inputs
Data Inputs/Outputs
Chip Enable Input
Write Enable Input
Output Enable Input
Lower-Byte Control
High-Byte Control
Power Supply
Ground
No Connection
FUNCTIONAL BLOCK DIAGRAM
A0
A1
A2
A3
A4
A8
A12
A13
A14
A15
I/O1
I/O16
I/O
ROW
DECODER
.
MEMORY ARRAY
.
.
1024 Rows x 64 Columns x 16 bits
.
.
.
.
.
.
CONTROL
.
.
.
.
.
.
COLUMN I/O
CE
WE
OE
COLUMN DECODER
LOGIC
CONTROL
LB
UB
A11 A10
A9
A7 A6 A5
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882
FAX: 886-3-5777919
P80073
1
UTRON
Preliminary Rev. 0.1
64K X 16 BIT LOW POWER CMOS SRAM
UT62L6416
PIN CONFIGURATION
A4
A3
A2
A1
A0
A5
A6
A7
OE
UB
1
2
3
4
5
6
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A
B
C
D
E
F
G
H
LB
I/O9
I/O10
OE
UB
I/O11
I/O12
I/O13
A0
A3
A5
NC
NC
A14
A12
A9
A1
A4
A6
A7
NC
A15
A13
A10
A2
CE
I/O2
I/O4
I/O5
I/O6
NC
I/O1
I/O3
Vcc
Vss
I/O7
I/O8
NC
CE
I/O1
I/O2
I/O3
I/O4
Vcc
Vss
I/O5
I/O6
I/O7
I/O8
WE
LB
I/O16
I/O15
I/O14
I/O13
Vss
Vcc
I/O12
I/O11
I/O10
I/O9
NC
A8
A9
A10
A11
NC
UT62L6416
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
Vss
Vcc
I/O15
I/O16
I/O14
NC
A8
WE
A11
NC
A15
A14
A13
A12
NC
1
2
3
4
5
6
TFBGA
TSOP II
TRUTH TABLE
MODE
Standby
Output
Disable
Read
CE
OE
X
X
H
H
L
L
L
X
X
X
WE
LB
UB
X
H
X
L
H
L
L
H
L
L
Write
H
X
L
L
L
L
L
L
L
L
X
X
H
H
H
H
H
L
L
L
X
H
L
X
L
H
L
L
H
L
SUPPLY CURRENT
I/O OPERATION
I/O1-I/O8 I/O9-I/O16
High – Z
High – Z
I
SB
, I
SB1
High – Z
High – Z
I
SB
, I
SB1
High – Z
High – Z
I
CC
,I
CC1
,I
CC2
High – Z
High – Z
D
OUT
High – Z
I
CC
,I
CC1
,I
CC2
High – Z
D
OUT
D
OUT
D
OUT
D
IN
High – Z
I
CC
,I
CC1
,I
CC2
High – Z
D
IN
D
IN
D
IN
Note:
H = V
IH
, L=V
IL
, X = Don't care.
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882
FAX: 886-3-5777919
P80073
2
UTRON
Preliminary Rev. 1.0
64K X 16 BIT LOW POWER CMOS SRAM
UT62L6416
ABSOLUTE MAXIMUM RATINGS*
PARAMETER
Terminal Voltage with Respect to V
SS
Operating Temperature
Commercial
Extended
Storage Temperature
Power Dissipation
DC Output Current
Soldering Temperature (under 10 secs)
SYMBOL
V
TERM
T
A
T
A
T
STG
P
D
I
OUT
Tsolder
RATING
-0.5 to 4.6
0 to 70
-20 to 80
-65 to +150
1
50
260
UNIT
V
℃
℃
℃
W
mA
℃
*Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a
stress rating only and functional operation of the device or any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device
reliability.
DC ELECTRICAL CHARACTERISTICS
(V
CC
= 2.7V~3.6V, TA = 0
℃
to 70
℃
/ -20
℃
to 80
℃
(E))
PARAMETER
MIN. TYP. MAX.
SYMBOL
TEST CONDITION
Power Voltage
V
CC
2.7 3.0
3.6
Input High Voltage
V
IH
2.2
-
V
CC
+0.3
Input Low Voltage
V
IL
-0.2
-
0.6
Input Leakage Current
I
LI
-1
-
1
V
SS
≦
V
IN
≦
V
CC
Output Leakage Current
I
LO
-1
-
1
V
SS
≦
V
I/O
≦
V
CC;
Output Disabled
Output High Voltage
V
OH
I
OH
= -1mA
2.2
-
-
Output Low Voltage
V
OL
I
OL
= 2 mA
-
-
0.4
Operating Power
I
CC
Cycle time=min, 100%duty,
55 -
30
45
Supply Current
70 -
25
35
I/O=0mA, CE =V
IL
;
100 -
20
25
Average Operation
Icc1
4
5
Cycle time=1µs,100%duty,I/O=0mA,
-
Current
CE
≦
0.2V,other pins at 0.2V or Vcc-0.2V,
Icc2
Standby Current (TTL)
Standby Current (CMOS)
I
SB
I
SB
1
Cycle time=500ns,100%duty,I/O=0mA,
-
UNIT
V
V
V
µA
µA
V
V
mA
mA
mA
mA
mA
mA
µA
µA
8
0.3
20
3
10
0.5
80
25
CE
≦
0.2V,other pins at 0.2V or Vcc-0.2V,
1. CE =V
IH,
other pins =V
IL
or V
IH
,
2. UB =
LB
= V
IH,
other pins =V
IL
or V
IH
,
-L
1. CE =V
CC
-0.2V,
other pins at 0.2V or Vcc-0.2V,
-LL
2. UB =
LB
=V
CC
-0.2V,
other pins at 0.2V or Vcc-0.2V,
-
-
-
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882
FAX: 886-3-5777919
P80073
3
UTRON
Preliminary Rev. 1.0
64K X 16 BIT LOW POWER CMOS SRAM
UT62L6416
CAPACITANCE
(TA=25
℃
, f=1.0MHz)
PARAMETER
Input Capacitance
Input/Output Capacitance
SYMBOL
C
IN
C
I/O
MIN.
-
-
MAX
6
8
UNIT
pF
pF
Note : These parameters are guaranteed by device characterization, but not production tested.
AC TEST CONDITIONS
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing Reference Levels
Output Load
0V to 3.0V
5ns
1.5V
C
L
= 30pF, I
OH
/I
OL
= -1mA / 2mA
AC ELECTRICAL CHARACTERISTICS
(V
CC
=2.7V~3.6V, TA =0
℃
to 70
℃
/ -20
℃
to 80
℃
(E))
(1) READ CYCLE
PARAMETER
Read Cycle Time
Address Access Time
Chip Enable Access Time
Output Enable Access Time
Chip Enable to Output in Low Z
Output Enable to Output in Low Z
Chip Disable to Output in High Z
Output Disable to Output in High Z
Output Hold from Address Change
LB
,
UB
Access Time
LB
,
UB
to High-Z Output
LB
,
UB
to Low-Z Output
SYMBOL
UT62L6416-55
UT62L6416-70
UT62L6416-100
UNIT
t
RC
t
AA
t
ACE
t
OE
t
CLZ*
t
OLZ*
t
CHZ*
t
OHZ*
t
OH
t
BA
t
BHZ
t
BLZ
MIN.
55
-
-
-
10
5
-
-
5
-
-
0
MAX.
-
55
55
30
-
-
20
20
-
55
25
-
MIN.
70
-
-
-
10
5
-
-
5
-
-
0
MAX.
-
70
70
35
-
-
25
25
-
70
30
-
MIN.
100
-
-
-
10
5
-
-
5
-
-
0
MAX.
-
100
100
50
-
-
30
30
-
100
40
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(2) WRITE CYCLE
PARAMETER
Write Cycle Time
Address Valid to End of Write
Chip Enable to End of Write
Address Set-up Time
Write Pulse Width
Write Recovery Time
Data to Write Time Overlap
Data Hold from End of Write Time
Output Active from End of Write
Write to Output in High Z
SYMBOL
UT62L6416-55
UT62L6416-70
UT62L6416-100
UNIT
LB
,
UB
Valid to End of Write
*These parameters are guaranteed by device characterization, but not production tested.
*55ns for Vcc=3.0V~3.6V
t
WC
t
AW
t
CW
t
AS
t
WP
t
WR
t
DW
t
DH
t
OW*
t
WHZ*
t
BW
MIN.
55
50
50
0
45
0
25
0
5
-
45
MAX.
-
-
-
-
-
-
-
-
-
30
-
MIN.
70
60
60
0
55
0
30
0
5
-
60
MAX.
-
-
-
-
-
-
-
-
-
30
-
MIN.
100
80
80
0
70
0
40
0
5
-
80
MAX.
-
-
-
-
-
-
-
-
-
40
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882
FAX: 886-3-5777919
P80073
4
UTRON
Preliminary Rev. 1.0
64K X 16 BIT LOW POWER CMOS SRAM
UT62L6416
TIMING WAVEFORMS
READ CYCLE 1
(Address Controlled)
(1,2,4)
t
RC
Address
t
AA
t
OH
t
OH
DOUT
Data Valid
READ CYCLE 2
(
CE
and
OE
Controlled)
(1,3,5,6)
t
Address
RC
CE
t
AA
t
ACE
t
OE
t
OLZ
t
BLZ
t
CHZ
OE
t
BA
OHZ
LB , UB
t
t
CLZ
t
OH
t
BHZ
Dout
HIGH-Z
Data Valid
HIGH-Z
Notes :
1.
WE
is HIGH for read cycle.
2. Device is continuously selected CE =V
IL.
3. Address must be valid prior to or coincident with CE transition; otherwise t
AA
is the limiting parameter.
4. OE is LOW.
5. t
CLZ
, t
OLZ
, t
CHZ
, t
OHZ,
t
BHZ
and t
BLZ
are specified with C
L
= 5pF. Transition is measured
±500mV
from steady state.
6. At any given temperature and voltage condition, t
CHZ
is less than t
CLZ
, t
OHZ
is less than t
OLZ.
, t
BHZ
is less than t
BLZ.
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882
FAX: 886-3-5777919
P80073
5
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