NXP Semiconductors
Data Sheet: Technical Data
Document Number MPC5746C
Rev. 6, 11/2018
MPC5746C Microcontroller
Datasheet
Features
• 1 × 160 MHz Power Architecture® e200z4 Dual issue,
32-bit CPU
– Single precision floating point operations
– 8 KB instruction cache and 4 KB data cache
– Variable length encoding (VLE) for significant code
density improvements
• 1 x 80 MHz Power Architecture® e200z2 Single issue,
32-bit CPU
– Using variable length encoding (VLE) for
significant code size footprint reduction
• End to end ECC
– All bus masters, for example, cores, generate a
single error correction, double error detection
(SECDED) code for every bus transaction
– SECDED covers 64-bit data and 29-bit address
• Memory interfaces
– 3 MB on-chip flash memory supported with the
flash memory controller
– 3 x flash memory page buffers (3-port flash memory
controller)
– 384 KB on-chip SRAM across three RAM ports
• Clock interfaces
– 8-40 MHz external crystal (FXOSC)
– 16 MHz IRC (FIRC)
– 128 KHz IRC (SIRC)
– 32 KHz external crystal (SXOSC)
– Clock Monitor Unit (CMU)
– Frequency modulated phase-locked loop (FMPLL)
– Real Time Counter (RTC)
• System Memory Protection Unit (SMPU) with up to 32
region descriptors and 16-byte region granularity
• 16 Semaphores to manage access to shared resources
• Interrupt controller (INTC) capable of routing
interrupts to any CPU
• Crossbar switch architecture for concurrent access to
peripherals, flash memory, and RAM from multiple
bus masters
NXP reserves the right to change the production detail specifications as may be
required to permit improvements in the design of its products.
MPC5746C
• 32-channel eDMA controller with multiple transfer
request sources using DMAMUX
• Boot Assist Flash (BAF) supports internal flash
programming via a serial link (SCI)
• Analog
– Two analog-to-digital converters (ADC), one 10-bit
and one 12-bit
– Three analog comparators
– Cross Trigger Unit to enable synchronization of
ADC conversions with a timer event from the
eMIOS or from the PIT
• Communication
– Four Deserial Serial Peripheral Interface (DSPI)
– Four Serial Peripheral interface (SPI)
– 16 serial communication interface (LIN) modules
– Eight enhanced FlexCAN3 with FD support
– Four inter-IC communication interface (I2C)
– ENET complex (10/100 Ethernet) that supports
Multi queue with AVB support, 1588, and MII/
RMII
– Dual-channel FlexRay controller
• Audio
– Synchronous Audio Interface (SAI)
– Fractional clock dividers (FCD) operating in
conjunction with the SAI
• Configurable I/O domains supporting FlexCAN,
LINFlexD, Ethernet, and general I/O
• Supports wake-up from low power modes via the
WKPU controller
• On-chip voltage regulator (VREG)
• Debug functionality
– e200z2 core:NDI per IEEE-ISTO 5001-2008
Class3+
– e200z4 core: NDI per IEEE-ISTO 5001-2008 Class
3+
• Timer
– 16 Periodic Interrupt Timers (PITs)
– Two System Timer Modules (STM)
– Three Software Watchdog Timers (SWT)
– 64 Configurable Enhanced Modular Input Output Subsystem (eMIOS) channels
• Device/board boundary Scan testing supported with Joint Test Action Group (JTAG) of IEEE 1149.1 and IEEE 1149.7
(CJTAG)
• Security
– Hardware Security Module (HSMv2)
– Password and Device Security (PASS) supporting advanced censorship and life-cycle management
– One Fault Collection and Control Unit (FCCU) to collect faults and issue interrupts
• Functional Safety
– ISO26262 ASIL-B compliance
• Multiple operating modes
– Includes enhanced low power operation
MPC5746C Microcontroller Datasheet, Rev. 6, 11/2018
2
NXP Semiconductors
Table of Contents
1
2
3
Block diagram.................................................................................... 4
Family comparison.............................................................................4
Ordering parts.....................................................................................8
3.1
3.2
4
Determining valid orderable parts ..........................................8
Ordering Information ............................................................. 9
6.3.3
6.3.4
6.3.5
6.3.6
6.3.2
Flash memory Array Integrity and Margin Read
specifications.......................................................... 39
Flash memory module life specifications............... 40
Data retention vs program/erase cycles.................. 40
Flash memory AC timing specifications................ 41
Flash read wait state and address pipeline control
settings ................................................................... 42
6.4
Communication interfaces.......................................................43
6.4.1
6.4.2
DSPI timing............................................................ 43
FlexRay electrical specifications............................ 49
6.4.2.1
6.4.2.2
6.4.2.3
6.4.2.4
6.4.3
6.4.4
6.5
FlexRay timing....................................49
TxEN................................................... 49
TxD..................................................... 50
RxD..................................................... 51
General............................................................................................... 9
4.1
4.2
4.3
4.4
4.5
4.6
4.7
Absolute maximum ratings..................................................... 9
Recommended operating conditions....................................... 11
Voltage regulator electrical characteristics............................. 13
Voltage monitor electrical characteristics............................... 17
Supply current characteristics................................................. 18
Electrostatic discharge (ESD) characteristics......................... 22
Electromagnetic Compatibility (EMC) specifications............ 22
5
I/O parameters....................................................................................23
5.1
5.2
5.3
5.4
5.5
5.6
AC specifications @ 3.3 V Range...........................................23
DC electrical specifications @ 3.3V Range............................24
AC specifications @ 5 V Range..............................................25
DC electrical specifications @ 5 V Range..............................25
Reset pad electrical characteristics..........................................26
PORST electrical specifications..............................................28
Ethernet switching specifications........................... 52
SAI electrical specifications .................................. 53
Debug specifications............................................................... 55
6.5.1
6.5.2
6.5.3
6.5.4
JTAG interface timing ........................................... 55
Nexus timing...........................................................58
WKPU/NMI timing................................................ 60
External interrupt timing (IRQ pin)........................ 61
6
Peripheral operating requirements and behaviours............................ 28
6.1
Analog..................................................................................... 28
6.1.1
6.1.2
ADC electrical specifications................................. 28
Analog Comparator (CMP) electrical
specifications.......................................................... 33
6.2
Clocks and PLL interfaces modules........................................34
6.2.1
6.2.2
6.2.3
6.2.4
Main oscillator electrical characteristics.................34
32 kHz Oscillator electrical specifications ............ 36
16 MHz RC Oscillator electrical specifications......36
128 KHz Internal RC oscillator Electrical
specifications ......................................................... 37
6.2.5
6.3
PLL electrical specifications ..................................37
9
8
7
Thermal attributes.............................................................................. 61
7.1
Thermal attributes................................................................... 61
Dimensions.........................................................................................65
8.1
Obtaining package dimensions ...............................................65
Pinouts................................................................................................66
9.1
Package pinouts and signal descriptions................................. 66
10 Reset sequence................................................................................... 66
10.1 Reset sequence........................................................................ 66
10.1.1
10.1.2
10.1.3
Reset sequence duration..........................................66
BAF execution duration..........................................66
Reset sequence description..................................... 67
Memory interfaces...................................................................38
6.3.1
Flash memory program and erase specifications.... 38
11 Revision History.................................................................................69
11.1 Revision History......................................................................69
MPC5746C Microcontroller Datasheet, Rev. 6, 11/2018
NXP Semiconductors
3
Block diagram
1 Block diagram
160 MHz e200z4
80 MHz e200z2
64-bit AHB
8 KB i-cache 4 KB d-cache
SPFP-APU
E2 E-ECC
Nexus 3+
64-bit AHB
E2 E-ECC
Nexus 3+
Ethernet
(ENET)
eDMA
HSMv2
Flexray
FMPLL
RTC/API
2 x SWTs
64-bit data
E2 E-ECC
SMPU
16 x SEMA42
16 x PIT-RTI
Flash Memory
E2 E-ECC
3 x SA-PF buffers
Triple ported
3 MB array (inc EEE)
2xRAM
Peripheral
bridge
E2 E-ECC
Low power
unit interface
(LPU)
32 KHz
SXOSC
16 MHz FIRC
DEBUG/
JTAG
FCCU
PASS
SSCM
MC_CGM,
MC_PCU,
MC_ME,
MC_RGM
SIUL
STCU
(MBIST)
CMU
TDM
System bus masters
System
WKPU
BAF
2 x STM
PMC
E2 E-ECC
64-bit wide RAM
256 KB array
256 KB array
128 KHz
SIRC
8–40 MHz
FXOSC
MEMU
Peripheral clusters
68 ch 10-bit ADC0 31 ch 12-bit ADC1 1 x FlexCAN(PN)*
(mix int and ext)
7 x FlexCAN*
4 x I
2
C
2 x eMIOS + BCTU
3 x analog
comparator (CMP)
2-core INTC
4 x DSPI
4 x SPI
DMA and
2 x channel mux
16 x LINFlexD
3 x SAI
3 x FCD
1 x CRC
Padkeeper
support
Register
protection
*
All FlexCANs optionally support
CAN FD
Figure 1. MPC5746C block diagram
2 Family comparison
The following table provides a summary of the different members of the MPC5746C
family and their proposed features. This information is intended to provide an
understanding of the range of functionality offered by this family. For full details of all of
the family derivatives please contact your marketing representative.
MPC5746C Microcontroller Datasheet, Rev. 6, 11/2018
4
NXP Semiconductors
Family comparison
NOTE
All optional features (Flash memory, RAM, Peripherals) start
with lowest number or address (e.g., FlexCAN0) and end at
highest available number or address (e.g., MPC574xB/C have 6
CAN, ending with FlexCAN5).
Table 1. MPC5746C Family Comparison1
Feature
CPUs
FPU
Maximum
Operating
Frequency
2
Flash memory
EEPROM
support
RAM
256 KB
MPC5745B
e200z4
e200z4
160MHz (Z4)
MPC5744B
e200z4
e200z4
160MHz (Z4)
MPC5746B
e200z4
e200z4
160MHz (Z4)
MPC5744C
e200z4
e200z2
e200z4
160MHz (Z4)
80MHz (Z2)
2 MB
1.5 MB
Emulated up to 64K
192 KB
384 KB
(Optional
512KB)
3
16 entry
32 channels
36 Standard channels
32 External channels
12-bit ADC
Analog
Comparator
BCTU
SWT
STM
PIT-RTI
RTC/API
Total Timer I/O
5
LINFlexD
1
Master and Slave (LINFlexD[0], 11 Master
(LINFlexD[1:11])
FlexCAN
DSPI/SPI
6 with optional CAN FD support (FlexCAN[0:5])
4 x DSPI
4 x SPI
Table continues on the next page...
1, SWT[0]
1, STM[0]
16 channels PIT
1 channels RTI
1
64 channels
16-bits
1
Master and Slave (LINFlexD[0], 15 Master
(LINFlexD[1:15])
8 with optional CAN FD support (FlexCAN[0:7])
15 Precision channels
16 Standard channels
3
1
2
4
2
192 KB
3 MB
1.5 MB
MPC5745C
e200z4
e200z2
e200z4
160MHz (Z4)
80MHz (Z2)
2 MB
Emulated up to 128K
256 KB
384 KB
(Optional
512KB)
3
MPC5746C
e200z4
e200z2
e200z4
160MHz (Z4)
80MHz (Z2)
3 MB
ECC
SMPU
DMA
10-bit ADC
End to End
MPC5746C Microcontroller Datasheet, Rev. 6, 11/2018
NXP Semiconductors
5
Microcontroller MCU
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