Features
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12.4 SPECint95, 8.4 SPECfp95 @ 266 MHz (TSPC750A) with 1 MB L2 @ 133 MHz
11.5 SPECint95, 6.9 SPECfp95 @ 266 MHz (TSPC740A)
488 MIPS @ 266 MHz
Selectable Bus Clock (11 CPU Bus Dividers up to 8x)
P
D
Typical 4,2 W @ 200 MHz, Full Operating Conditions
Nap, Doze and Sleep Modes for Power Savings
Superscalar (3 Instructions per Clock Cycle)
4G Byte Direct Addressing Range
64-bit Data and 32-bit Address Bus Interface
32 KB Instruction and Data Cache
Six Independent Execution Units and Two Register Files
Write-back and Write-through Operations
f
int
max = 266 MHz
f
bus
max = 83,3 MHz
Compatible CMOS Input / TTL Output
Description
The TSPC750A and TSPC740A microprocessor (after named 750A/740A) are low-
power implementations of the PowerPC Reduced Instruction Set Computer (RISC)
architecture.
The 750A/740A microprocessors designs are superscalar, capable of issuing three
instructions per clock cycle into six independent execution units
The 740A/750A microprocessors uses a 2,6/3,3-volts CMOS process technology and
maintains full interface compatibility with TTL devices.
The 750A/740A provides four software controllable power-saving modes and a ther-
mal assist unit management.
The 750A/740A microprocessors have separate 32K byte, physically-addressed
instruction and data caches and differ only in that the 750A features a dedicated L2
cache interface with on-chip L2 tags.
Both are software and bus-compatible with the PowerPC603 and PowerPC604 fami-
lies, and are fully JTAG compliant.
The TSPC740A microprocessor is pin compatible with the TSPC603e family.
G suffix
CBGA255 and CBGA360
Ceramic Ball Grid Array
GS suffix
CI-CBGA255 and CI-CBGA360
Ceramic Ball Grid Array
with Solder Column Interposer (SCI)
PowerPC
750A/740A RISC
Microprocessor
Family PID8t-
750A/740A
Specification
TSPC750A/740A
Rev. 2128A–11/01
1
Screening
This product is manufactured in full compliance with:
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CBGA upscreenings based upon ATMEL-Grenoble standards
Full military temperature range (Tc = -55°C,+125°C)
industrial temperature range (Tc = -40°C, +110°C)
CI-CGA versions of TSPC740A and TSPC750A (planned)
The TSPC750A is targeted for low power systems and supports the following power manage-
ment features—doze, nap, sleep, and dynamic power management. The TSPC750A consists
of a processor core and an internal L2 Tag combined with a dedicated L2 cache interface and
a 60x bus.
Simplified
Block Diagram
Figure 1.
TSPC750A Block Diagram
Instruction Fetch
Branch Unit
Completion
32K ICache
System Unit
Dispatch
BHT/BTIC
Control Unit
GPRs
FXU1
FXU2
Rename
Buffers
LSU
FPRs
Rename
Buffers
FPU
32K DCache
L2 Tags
L2 Cache
BIU
60x BIU
2
TSPC750A/740A
2128A–11/01
TSPC750A/740A
General
Parameters
Technology
Die Size
Transistor Count
Logic Design
Packages L2
The general parameters of the 750A/740A are the following:
0.29 mm CMOS, five-layer metal
7.56 mm x 8.79 mm (67 mm
2
)
6.35 million
Fully-static
740A: Surface mount 255 ceramic ball grid array (CBGA) and column interposer ceramic grid
array CI-CGA without L2interface
750A: Surface mount 360 ceramic ball grid array (CBGA) and column interposer ceramic grid
array CI-CGA with L2 interface
Core Power Supply
I/O Power Supply
2.6V
±
100 mV
3.3V
±
5% Vdc
Except L2 cache interface that is not supported by the PowerPC version, the major features
implemented in the PowerPC750A architecture are as follow:
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Branch Processing
Unit
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Internal L2 cache controller and 4K-entry tags; external data SRAMs
256K, 512K, and 1M byte 2-way set associative L2 cache support
Copy-back or write-through data cache (on a page basis, or for all L2)
64-byte (256K/512K) and 128-byte (1M byte) sectored line size
Supports flow-through (reg-buf) synchronous burst SRAMs, pipelined (reg-reg)
synchronous burst SRAMs, and pipelined (reg-reg) late-write synchronous burst SRAMs
Core-to-L2 frequency divisors of
÷1, ÷1.5, ÷2, ÷2.5,
and
÷3
supported
Four instructions fetched per clock
One branch processed per cycle (plus resolving 2 speculations)
Up to 1 speculative stream in execution, 1 additional speculative stream in fetch
512-entry branch history table (BHT) for dynamic prediction
64-entry, 4-way set associative branch target instruction cache (BTIC) to minimize branch
delay slots
Full hardware detection of dependencies (resolved in the execution units)
Dispatch two instructions to six independent units (system, branch, load/store, fixed-point
unit 1, fixed-point unit 2, or floating-point)
Serialization control (predispatch, postdispatch, execution serialization)
One cycle load or store cache access (byte, half-word, word, double-word)
Effective address generation
Hits under misses (one outstanding miss)
Single-cycle misaligned access within double word boundary
Alignment, zero padding, sign extend for integer register file
Floating-point internal format conversion (alignment, normalization)
Sequencing for load/store multiples and string operations
Store gathering
Cache and TLB instructions
Features
Level 2 (L2) Cache
Interface (not
implemented on
TSPC740A)
Dispatch Unit
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Load/store Unit
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2128A–11/01
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Fixed-point Units
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Bus Interface
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Big- and little-endian byte addressing supported
Misaligned little-endian support in hardware
Fixed-point unit 1 (FXU1)-multiply, divide, shift, rotate, arithmetic, logical
Fixed-point unit 2 (FXU2)-shift, rotate, arithmetic, logical
Single-cycle arithmetic, shift, rotate, logical
Multiply and divide support (multi-cycle)
Early out multiply
Compatible with 60x processor interface
32-bit address bus
64-bit data bus
Bus-to-core frequency multipliers of 3x, 3.5x, 4x, 4.5x, 5x, 5.5x, 6x, 6.5x, 7x, 7.5x, 8x
supported
Register file access
Forwarding control
Partial instruction decode
Support for IEEE-754 standard single- and double-precision floating-point arithmetic
3 cycle latency, 1 cycle throughput, single-precision multiply-add
3 cycle latency, 1 cycle throughput, double-precision add
4 cycle latency, 2 cycle throughput, double-precision multiply-add
Hardware support for divide
Hardware support for denormalized numbers
Time deterministic non-IEEE mode
Executes CR logical instructions and miscellaneous system instructions
Special register transfer instructions
32K, 32-byte line, 8-way set associative instruction cache
32K, 32-byte line, 8-way set associative data cache
Single-cycle cache access
Pseudo-LRU replacement
Copy-back or write-through data cache (on a page per page basis)
Supports all PowerPC memory coherency modes
Non-blocking instruction and data cache (one outstanding miss under hits)
No snooping of instruction cache
128 entry, 2-way set associative instruction TLB
128 entry, 2-way set associative data TLB
Hardware reload for TLBs
4 instruction BATs and 4 data BATs
Virtual memory support for up to 4 exabytes (2
52
) of virtual memory
Real memory support for up to 4 gigabytes (2
32
) of physical memory
Decode
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Floating-point Unit
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System Unit
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Cache Structure
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Memory Management
Unit
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4
TSPC750A/740A
2128A–11/01
TSPC750A/740A
Testability
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Integrated Power
Management
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Integrated Thermal
Management Assist
Unit
Reliability and
Serviceability
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LSSD scan design
JTAG interface
Low-power 2.6/3.3-volt design
Three static power saving modes: doze, nap, and sleep
Automatic dynamic power reduction when internal functional units are idle
On-chip thermal sensor and control logic
Thermal Management Interrupt for software regulation of junction temperature.
Parity checking on 60x and L2 cache buses
Pin Assignments
TSPC740A
Package
The pinout of the TSPC740A, 255 CBGA and CI-CGA packages as viewed from the top
surface.
5
2128A–11/01
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