200pin Unbuffered DDR2 SDRAM SO-DIMMs based on 512 Mb C ver.
This Hynix unbuffered Small Outline Dual In-Line Memory Module (DIMM) series consists of 512Mb C ver. DDR2
SDRAMs in Fine Ball Grid Array (FBGA) packages on a 200pin glass-epoxy substrate. This Hynix 512Mb C ver. based
Unbuffered DDR2 SO-DIMM series provide a high performance 8 byte interface in 67.60mm width form factor of indus-
try standard. It is suitable for easy interchange and addition.
FEATURES
•
JEDEC standard Double Data Rate2 Synchronous
DRAMs (DDR2 SDRAMs) with 1.8V +/- 0.1V Power
Supply
All inputs and outputs are compatible with SSTL_1.8
interface
Posted CAS
Programmable CAS Latency 3, 4, 5, 6
OCD (Off-Chip Driver Impedance Adjustment) and
ODT (On-Die Termination)
Fully differential clock operations (CK & CK)
•
•
•
•
•
•
•
Programmable Burst Length 4 / 8 with both sequen-
tial and interleave mode
Auto refresh and self refresh supported
8192 refresh cycles / 64ms
Serial presence detect with EEPROM
DDR2 SDRAM Package: 60ball(x8), 84ball(x16)
FBGA
67.60 x 30.00 mm form factor
Lead-free Products are RoHS compliant
•
•
•
•
•
ORDERING INFORMATION
Part Name
HYMP532S64CP6-E3/C4/Y5
HYMP564S64CP6-E3/C4/Y5
HYMP512S64CP8-E3/C4/Y5
HYMP532S64CLP6-E3/C4/Y5
HYMP564S64CLP6-E3/C4/Y5
HYMP512S64CLP8-E3/C4/Y5
Density
256MB
512MB
1GB
256MB
512MB
1GB
Organization
32Mx64
64Mx64
128Mx64
32Mx64
64Mx64
128Mx64
# of
DRAMs
4
8
16
4
8
16
# of
ranks
1
2
2
1
2
2
Materials
Lead free*
Lead free
Lead free
Lead free
Lead free
Lead free
Power
Consumption
Normal
Normal
Normal
Low
Low
Low
Notes:
1. All Hynix’ DDR2 Lead-free parts are compliant to RoHS.
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev. 0.6 / Dec. 2008
1
1200pin
Unbuffered DDR2 SDRAM SO-DIMMs
PIN DESCRIPTION
Symbol
Type
Polarity
Cross
Point
Pin Description
The system clock inputs. All address and commands lines are sampled on the cross point
of the rising edge of CK and falling edge of CK. A Delay Locked Loop (DLL) circuit is driven
from the clock inputs and output timing for read operations is synchronized to the input
clock.
Activates the DDR2 SDRAM CK signal when high and deactivates the CK signal when low.
By deactivating the clocks, CKE low initiates the Power Down mode or the Self Refresh
mode.
Enables the associated DDR2 SDRAM command decoder when low and disables the com-
mand decoder when high. When the command decoder is disabled, new commands are
ignored but previous operations continue. Rank 0 is selected by S0; Rank 1 is selected by
S1
When sampled at the cross point of the rising edge of CK and falling edge of CK, CAS, RAS
and WE define the operation to be executed by the SDRAM.
Selects which DDR2 SDRAM internal bank of four is activated.
Active
High
Asserts on-die termination for DQ, DM, DQS and DQS signals if enabled via the DDR2
SDRAM mode register.
During a Bank Activate command cycle, defines the row address when sampled at the
cross point of the rising edge of CK and falling edge of CK. During a Read or Write com-
mand cycle, defines the column address when sampled at the cross point of the rising
edge of CK and falling edge of CK. In addition to the column address, AP is used to invoke
autoprecharge operation at the end of the burst read or write cycle. If AP is high., autopre-
charge is selected and BA0-BAn defines the bank to be precharged. If AP is low, autopre-
charge is disabled. During a Precharge command cycle., AP is used in conjunction with
BA0-BAn to control which bank(s) to precharge. If AP is high, all banks will be precharged
regardless of the state of BA0-BAn inputs. If AP is low, then BA0-BAn are used to define
which bank to precharge.
Data Input/Output pins.
Active
High
The data write masks, associated with one data byte. In Write mode, DM operates as a
byte mask by allowing input data to be written if it is low but blocks the write operation if
it is high. In Read mode, DM lines have no effect.
The data strobe, associated with one data byte, sourced whit data transfers. In Write
mode, the data strobe is sourced by the controller and is centered in the data window. In
Read mode, the data strobe is sourced by the DDR2 SDRAMs and is sent at leading edge
of the data window. DQS signals are complements, and timing is relative to the crosspoint
of respective DQS and DQS. If the module is to be operated in single ended strobe mode,
all DQS signals must be tied on the system board to VSS and DDR2 SDRAM mode registers
programmed appropriately.
Power supplies for core, I/O, Serial Presense Detect, and ground for the module.
This is a bidirectional pin used to transfer data into or out of the SPD EEPROM. A resister
must be connected to V
DD t
o act as a pull up.
This signals is used to clock data into and out of the SPD EEPROM. A resistor may be con-
nected from SCL to VDD to act as a pull up.
Address pins used to select the Serial Presence Detect base address.
The TEST pin is reserved for bus analysis tools and is not connected on normal memory
modules (SODIMMs).
CK[1:0], CK[1:0]
Input
CKE[1:0]
Input
Active
High
S[1:0]
Input
Active
Low
Active
Low
RAS, CAS, WE
BA[1:0]
ODT[1:0]
Input
Input
Input
A[9:0], A10/AP,
A[15:11]
Input
DQ[63:0]
DM[7:0]
In/Out
Input
DQS[7:0], DQS[7:0] In/Out
Cross
point
V
DD
, V
DD
SPD,V
SS
SDA
SCL
SA[1:0]
TEST
Supply
In/Out
Input
Input
In/Out
Rev. 0.6 / Dec. 2008
3
DSP and ARM Processors
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