Latch-Up Current ..................................................... >200 mA
Operating Range
Range
Commercial
Industrial
Automotive
Ambient
Temperature (T
A
)
[3]
0°C to +70°C
–40°C to +85°C
–40°C to +125°C
V
CC
5V
±
10%
5V
±
10%
5V
±
10%
Electrical Characteristics
Over the Operating Range
Parameter
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
CC
I
SB1
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
[2]
Input Leakage Current
Output Leakage Current
V
CC
Operating
Supply Current
Automatic CE
Power Down Current —TTL
Inputs
Automatic CE
Power Down Current
—CMOS Inputs
GND < V
I
< V
CC
GND < V
I
< V
CC
,
Output Disabled
Com’l/Ind’l
Auto
Com’l/Ind’l
Auto
140
40
–1
+1
Test
Conditions
V
CC
= Min., I
OH
= –4.0 mA
V
CC
= Min., I
OL
= 8.0 mA
2.2
–0.5
–1
-12
Min.
2.4
0.4
6.0
0.8
+1
2.2
–0.5
–1
–4
–1
–4
Max.
Min.
2.4
0.4
6.0
0.8
+1
+4
+1
+4
130
130
40
50
10
0.5
10
15
0.5
-15
Max.
Unit
V
V
V
V
µA
µA
µA
µA
mA
mA
mA
mA
mA
mA
mA
V
CC
= Max., I
OUT
= 0 mA, Com’l/Ind’l
f = f
MAX
= 1/t
RC
Auto
Max. V
CC
, CE > V
IH
Com’l/Ind’l
V
IN
> V
IH
or V
IN
< V
IL
, f =
Auto
f
MAX
Max. V
CC
, CE > V
CC
–
0.3V, V
IN
> V
CC
– 0.3V,
or V
IN
< 0.3V, f = 0
Com’l/Ind’l
Auto
L Version
I
SB2
Capacitance
[4]
Parameter
C
IN
C
OUT
Description
Input Capacitance
Output Capacitance
Test Conditions
T
A
= 25°C, f = 1 MHz,
V
CC
= 5.0V
Max.
8
8
Unit
pF
pF
Thermal Resistance
[4]
Parameter
Description
Test Conditions
44-pin SOJ
64.32
31.03
44-pin
TSOP-II
76.89
14.28
Unit
°C/W
°C/W
Θ
JA
Θ
JC
Thermal Resistance Test conditions follow standard test methods and
(Junction to Ambient) procedures for measuring thermal impedance,
Thermal Resistance per EIA/JESD51.
(Junction to Case)
Notes:
2. V
IL
(min.) = –2.0V and V
IH
(max) = V
CC
+ 0.5V for pulse durations of less than 20 ns.
3. T
A
is the “Instant On” case temperature.
4. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05145 Rev. *C
Page 3 of 10
CY7C1021B
AC Test Loads and Waveforms
5V
OUTPUT
30 pF
INCLUDING
JIG AND
SCOPE
(a)
OUTPUT
Equivalent to: THÉVENIN
EQUIVALENT
R2
255Ω
R 481Ω
5V
OUTPUT
5 pF
INCLUDING
JIG AND
SCOPE
(b)
167
30 pF
1.73V
R2
255Ω
GND
R 481Ω
3.0V
90%
10%
ALL INPUT PULSES
90%
10%
Rise Time: 1 V/ns
Fall Time: 1 V/ns
Switching Characteristics
Over the Operating Range
[5]
7C1021B-12
Parameter
Read Cycle
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
t
DBE
t
LZBE
t
HZBE
Write Cycle
[8]
t
WC
t
SCE
t
AW
t
HA
t
SA
t
SD
t
HD
t
LZWE
t
HZWE
t
BW
Write Cycle Time
CE LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
Data Set-Up to Write End
Data Hold from Write End
WE HIGH to Low Z
[6]
WE LOW to High Z
[6, 7]
Byte Enable to End of Write
8
12
9
8
0
0
6
0
3
6
9
15
10
10
0
0
8
0
3
7
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
[6]
OE HIGH to High Z
[6, 7]
CE LOW to Low Z
[6]
CE HIGH to High Z
[6, 7]
CE LOW to Power-Up
CE HIGH to Power-Down
Byte Enable to Data Valid
Byte Enable to Low Z
Byte Disable to High Z
0
6
0
12
6
0
7
3
6
0
15
7
0
6
3
7
3
12
6
0
7
12
12
3
15
7
15
15
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Description
Min.
Max.
7C1021B-15
Min.
Max.
Unit
Notes:
5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
OL
/I
OH
and 30-pF load capacitance.
6. At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any given device.
7. t
HZOE
, t
HZBE
, t
HZCE
, and t
HZWE
are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured
±500
mV from steady-state voltage.
8. The internal write time of the memory is defined by the overlap of CE LOW, WE LOW and BHE/BLE LOW. CE, WE and BHE/BLE must be LOW to initiate a write, and
the transition of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
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