CXK77P36E160GB-43BF datasheet, PDF

Datasheet> All Categories > storage> storage> CXK77P36E160GB-43BF

CXK77P36E160GB-43BF: DescriptionStandard SRAM, 512KX36, 4.3ns, CMOS, PBGA119, 14 X 22 MM, 1.27 MM PITCH, BGA-119; Categorystorage storage; File Size257KB，25 Pages; ManufacturerSONY; Websitehttp://www.sony.co.jp

Download Datasheet Parametric View All

CXK77P36E160GB-43BF Overview

Standard SRAM, 512KX36, 4.3ns, CMOS, PBGA119, 14 X 22 MM, 1.27 MM PITCH, BGA-119

CXK77P36E160GB-43BF Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	SONY
Parts packaging code	BGA
package instruction	BGA, BGA119,7X17,50
Contacts	119
Reach Compliance Code	unknown
ECCN code	3A991.B.2.A
Maximum access time	4.3 ns
Spare memory width	36
Maximum clock frequency (fCLK)	232 MHz
I/O type	COMMON
JESD-30 code	R-PBGA-B119
JESD-609 code	e0
length	22 mm
memory density	18874368 bit
Memory IC Type	STANDARD SRAM
memory width	36
Number of functions	1
Number of terminals	119
word count	524288 words
character code	512000
Operating mode	SYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature
organize	512KX36
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Encapsulate equivalent code	BGA119,7X17,50
Package shape	RECTANGULAR
Package form	GRID ARRAY
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	240
power supply	1.9,3.3 V
Certification status	Not Qualified
Maximum seat height	2.5 mm
Maximum standby current	0.25 A
Minimum standby current	3.14 V
Maximum slew rate	0.75 mA
Maximum supply voltage (Vsup)	3.47 V
Minimum supply voltage (Vsup)	3.13 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	OTHER
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	BALL
Terminal pitch	1.27 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	10
width	14 mm

Preview

Download Datasheet

View All

SONY

CXK77P36E160GB / CXK77P18E160GB

4/42/43/44

Preliminary

16Mb LW R-L HSTL High Speed Synchronous SRAMs (512K x 36 or 1M x 18)

8Mb LW R-L w/ EC HSTL High Speed Synchronous SRAMs (256K x 36 or 512K x 18)

Description

The CXK77P36E160GB (organized as 524,288 words by 36 bits) and the CXK77P18E160GB (organized as 1,048,576 words

by 18 bits) are high speed CMOS synchronous static RAMs with common I/O pins. These synchronous SRAMs integrate input

registers, high speed RAM, output latches, and a one-deep write buffer onto a single monolithic IC. Register - Latch (R-L) read

operations and Late Write (LW) write operations are supported, providing a high-performance user interface.

Two distinct R-L modes of operation are supported, selectable via the M2 mode pin. When M2 is “high”, these devices function

as conventional 16Mb R-L SRAMs, and pin 2B functions as a conventional SA address input. When M2 is “low”, these devices

function as Error-Correcting (EC) 8Mb R-L SRAMs, and pin 2B is ignored.

When Error-Correcting 8Mb R-L mode is selected, the SRAM is divided into two banks internally - a “primary” bank and a

“secondary” bank. During write operations, input data is ultimately written to both banks internally (through one stage of write

pipelining). During read operations, data is read from both banks internally, and each byte of primary bank data is individually

parity-checked. If the parity of a particular byte of primary data is correct (that is, “odd”), it is driven valid externally. If the

parity of a particular byte of primary data is incorrect (that is, “even”), it is discarded, and the corresponding byte of secondary

bank data is driven valid externally. Primary / secondary bank data selection is performed on each data byte independently.

Data read from the secondary bank is NOT parity-checked.

Data read from the write buffer is NOT parity-checked.

All address and control input signals except ZZ (Sleep Mode) are registered on the rising edge of K (Input Clock).

During read operations, output data is driven valid from the falling edge of K, one half clock cycle after the address is registered.

During write operations, input data is registered on the rising edge of K, one full clock cycle after the address is registered.

The output drivers are series terminated, and the output impedance is programmable through an external impedance matching

resistor RQ. By connecting RQ between ZQ and V

, the output impedance of all DQ pins can be precisely controlled.

Sleep (power down) mode control is provided through the asynchronous ZZ input. 250 MHz operation is obtained from a single

3.3V power supply. JTAG boundary scan interface is provided using a subset of IEEE standard 1149.1 protocol.

Features

•

4 Speed Bins

-4 (-4A) (-4B)

-42 (-42A) (-42B)

-43 (-43A) (-43B)

-44

Cycle Time / Access Time

4.0ns / 3.9ns (3.8ns) (3.7ns)

4.2ns / 4.2ns (4.1ns) (4.0ns)

4.3ns / 4.5ns (4.4ns) (4.3ns)

4.4ns / 4.7ns

•

Single 3.3V power supply (V

): 3.3V

Dedicated output supply voltage (V

DDQ

): 1.9V typical

HSTL-compatible I/O interface with dedicated input reference voltage (V

REF

): 0.85V typical

Late Write (LW) write operations

Conventional 16Mb or Error-Correcting (EC) 8Mb mode of operation, selectable via dedicated mode pin (M2)

Full read/write coherency

Byte Write capability

One cycle deselect

Differential input clocks (K/K)

Programmable impedance output drivers

Sleep (power down) mode via dedicated mode pin (ZZ)

JTAG boundary scan (subset of IEEE standard 1149.1)

119 pin (7x17), 1.27mm pitch, 14mm x 22mm Ball Grid Array (BGA) package

16Mb LW R-L and 8Mb LW R-L w/ EC, rev 1.1

1 / 25

March 2, 2001

Recommended Resources

Temperature sensor resistance compensation circuit

Radio recorder AC power supply alarm circuit

Sony KV-25F color TV power supply circuit

555 natural wind circuit with long timing

Sine wave square-triangle wave oscillator with linear/logarithmic sweep

Pin function diagram of VD5026/27

EEWORLD University Hall----labview2016: labview2016：https://training.eeworld.com.cn/course/5837Labview allows you to implement simple programs and intuitive interface experience...; 开心萝卜 Automotive Electronics

Simulation and Calculation in PCB Circuit Design: There are many different types of simulation software on the market, all of which are helpful to PCB designers. Each tool has its own capabilities and limitations, and understanding their basic charac...; btty038 PCB Design

SAIL-IMX6Q AD7606 module debugging record: 1 This article summarizes the process of debugging the AD7606 module, the problems encountered and the solutions. The main problems occurred in the hardware welding, including welding chips, surface m...; 电鱼电子工程师 Integrated technical exchanges

Read the good book "Operational Amplifier Parameter Analysis and LTspice Application Simulation" 04 Amplifier Noise Evaluation Case: [i=s]This post was last edited by 1nnocent on 2021-5-19 16:49[/i]Since I have had little exposure to weak signal amplification before, I don’t know much about this area. Now follow the example in 2.7....; 1nnocent Analog electronics

Request a circuit diagram: This is the original post https://en.eeworld.com/bbs/forum.php?mod=viewthread&tid=326800&extra=&page=1 I have always wanted to make a digital tube clock, but I am a novice. Please follow this program ...; 365℃ MCU

Program-controlled constant current source simulation is incorrect: I would like to ask what is the function of u3a, and the current value of the simulation result is too small, and no matter how I adjust the input, the current does not change...; 电子dd Power technology

Shortcut: A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP AQ AR AS AT AU AV AW AX AY AZ B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF BG BH BI BJ BK BL BM BN BO BP BQ BR BS BT BU BV BW BX BY BZ C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF CG CH CI CJ CK CL CM CN CO CP CQ CR CS CT CU CV CW CX CY CZ D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF DG DH DI DJ DK DL DM DN DO DP DQ DR DS DT DU DV DW DX DZ

Popular Components