PIC18(L)F26/45/46K40
28/40/44-Pin, Low-Power, High-Performance
Microcontrollers with XLP Technology
Description
These PIC18(L)F26/45/46K40 microcontrollers feature Analog, Core Independent Peripherals and
Communication Peripherals, combined with eXtreme Low-Power (XLP) technology for a wide range of
general purpose and low-power applications. These 28/40/44 -pin devices are equipped with a 10-bit
ADC with Computation (ADCC) automating Capacitive Voltage Divider (CVD) techniques for advanced
touch sensing, averaging, filtering, oversampling and performing automatic threshold comparisons. They
also offer a set of Core Independent Peripherals such as Complementary Waveform Generator (CWG),
Windowed Watchdog Timer (WWDT), Cyclic Redundancy Check (CRC)/Memory Scan, Zero-Cross
Detect (ZCD) and Peripheral Pin Select (PPS), providing for increased design flexibility and lower system
cost.
Core Features
•
•
C Compiler Optimized RISC Architecture
Operating Speed:
– DC – 64 MHz clock input over the full V
DD
range
– 62.5 ns minimum instruction cycle
Programmable 2-Level Interrupt Priority
31-Level Deep Hardware Stack
Three 8-Bit Timers (TMR2/4/6) with Hardware Limit Timer (HLT)
Four 16-Bit Timers (TMR0/1/3/5)
Low-Current Power-on Reset (POR)
Power-up Timer (PWRT)
Brown-out Reset (BOR)
Low-Power BOR (LPBOR) Option
Windowed Watchdog Timer (WWDT):
–
–
–
–
Watchdog Reset on too long or too short interval between watchdog clear events
Variable prescaler selection
Variable window size selection
All sources configurable in hardware or software
•
•
•
•
•
•
•
•
•
Memory
•
•
•
Up to 64K bytes Program Flash Memory
Up to 3728 Bytes Data SRAM Memory
1024 Bytes Data EEPROM
©
2017 Microchip Technology Inc.
Datasheet
DS40001816E-page 1
PIC18(L)F26/45/46K40
•
•
Programmable Code Protection
Direct, Indirect and Relative Addressing modes
Operating Characteristics
•
Operating Voltage Ranges:
– 1.8V to 3.6V (PIC18LF26/45/46K40 )
– 2.3V to 5.5V ( PIC18F26/45/46K40)
Temperature Range:
– Industrial: -40°C to 85°C
–
Extended: -40°C to 125°C
•
Power-Saving Operation Modes
•
•
•
•
Doze: CPU and Peripherals Running at Different Cycle Rates (typically CPU is lower)
Idle: CPU Halted While Peripherals Operate
Sleep: Lowest Power Consumption
Peripheral Module Disable (PMD):
– Ability to selectively disable hardware module to minimize active power consumption of unused
peripherals
eXtreme Low-Power (XLP) Features
•
•
•
•
Sleep mode: 50 nA @ 1.8V, typical
Windowed Watchdog Timer: 500 nA @ 1.8V, typical
Secondary Oscillator: 500 nA @ 32 kHz
Operating Current:
– 8 uA @ 32 kHz, 1.8V, typical
– 32 uA/MHz @ 1.8V, typical
Digital Peripherals
•
Complementary Waveform Generator (CWG):
– Rising and falling edge dead-band control
– Full-bridge, half-bridge, 1-channel drive
– Multiple signal sources
Capture/Compare/PWM (CCP) modules:
– Two CCPs
– 16-bit resolution for Capture/Compare modes
– 10-bit resolution for PWM mode
10-Bit Pulse-Width Modulators (PWM):
– Two 10-bit PWMs
Serial Communications:
– Two Enhanced USART (EUSART) with Auto-Baud Detect, Auto-wake-up on Start.
RS-232, RS-485, LIN compatible
– SPI
•
•
•
©
2017 Microchip Technology Inc.
Datasheet
DS40001816E-page 2
PIC18(L)F26/45/46K40
•
– I
2
C, SMBus and PMBus
™
compatible
Up to 35 I/O Pins and One Input Pin:
– Individually programmable pull-ups
– Slew rate control
– Interrupt-on-change on most pins
– Input level selection control
Programmable CRC with Memory Scan:
– Reliable data/program memory monitoring for Fail-Safe operation (e.g., Class B)
– Calculate CRC over any portion of Flash or EEPROM
– High-speed or background operation
Hardware Limit Timer (TMR2/4/6+HLT):
–
•
•
Hardware monitoring and Fault detection
Peripheral Pin Select (PPS):
– Enables pin mapping of digital I/O
Data Signal Modulator (DSM)
•
•
Analog Peripherals
•
10-Bit Analog-to-Digital Converter with Computation (ADC
2
):
35 external channels
Conversion available during Sleep
Four internal analog channels
Internal and external trigger options
Automated math functions on input signals:
• Averaging, filter calculations, oversampling and threshold comparison
– 8-bit hardware acquisition timer
Hardware Capacitive Voltage Divider (CVD) Support:
– 8-bit precharge timer
– Adjustable sample and hold capacitor array
– Guard ring digital output drive
Zero-Cross Detect (ZCD):
– Detect when AC signal on pin crosses ground
5-Bit Digital-to-Analog Converter (DAC):
– Output available externally
– Programmable 5-bit voltage (% of V
DD
)
– Internal connections to comparators, Fixed Voltage Reference and ADC
Two Comparators (CMP):
– Four external inputs
– External output via PPS
Fixed Voltage Reference (FVR) module:
– 1.024V, 2.048V and 4.096V output levels
–
–
–
–
–
•
•
•
•
•
Clocking Structure
•
High-Precision Internal Oscillator Block (HFINTOSC):
©
2017 Microchip Technology Inc.
Datasheet
DS40001816E-page 3
PIC18(L)F26/45/46K40
– Selectable frequencies up to 64 MHz
– ±1% at calibration
32 kHz Low-Power Internal Oscillator (LFINTOSC)
External 32 kHz Crystal Oscillator (SOSC)
External High-frequency Oscillator Block:
– Three crystal/resonator modes
– Digital Clock Input mode
– 4x PLL with external sources
Fail-Safe Clock Monitor:
– Allows for safe shutdown if external clock stops
Oscillator Start-up Timer (OST)
•
•
•
•
•
Programming/Debug Features
•
•
•
In-Circuit Serial Programming
™
(ICSP
™
) via Two Pins
In-Circuit Debug (ICD) with Three Breakpoints via Two Pins
Debug Integrated On-Chip
PIC18(L)F26/45/46K40 Family Types
Table 1. Devices included in this data sheet
Peripheral Module Disable
Low Voltage Detect (LVD)
CRC with Memory Scan
Program Memory Flash
(bytes)
Temperature Indicator
Y
Y
Y
Temperature Indicator
Y
Y
Y
Y
Y
Windowed Watchdog
8-bit TMR with HLT
Zero-Cross Detect
Computation (ch)
10-bit ADC2 with
CCP/10-bit PWM
Data EEPROM
(bytes)
Comparators
16-bit Timers
Data SRAM
(bytes)
5-bit DAC
Device
PIC18(L)F26K40
PIC18(L)F45K40
PIC18(L)F46K40
64k
32k
64k
3615
2048
3615
1024
256
1024
25
36
36
4
4
4
2
2
2
24
35
35
1
1
1
1
1
1
2/2
2/2
2/2
1
1
1
0
0
0
1
1
1
3
3
3
Y
Y
Y
Y
Y
Y
2
2
2
2
2
2
Y
Y
Y
Y
Y
Y
Table 2. Devices not included in this data sheet
Peripheral Module Disable
Low Voltage Detect (LVD)
CRC with Memory Scan
Program Memory Flash
(bytes)
Windowed Watchdog
8-bit TMR with HLT
Zero-Cross Detect
Computation (ch)
10-bit ADC2 with
CCP/10-bit PWM
Data EEPROM
(bytes)
Comparators
16-bit Timers
Data SRAM
(bytes)
5-bit DAC
Device
PIC18(L)F24K40
PIC18(L)F25K40
PIC18(L)F27K40
PIC18(L)F47K40
PIC18(L)F65K40
16k
32k
128k
128k
32k
1024
2048
3615
3615
2048
256
256
1024
1024
1024
25
25
25
36
60
4
4
4
4
5
2
2
2
2
3
24
24
24
35
45
1
1
1
1
1
1
1
1
1
1
2/2
2/2
2/2
2/2
5/2
1
1
1
1
1
0
0
0
0
2
1
1
1
1
1
3
3
3
3
4
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
1
1
2
2
5
1
1
2
2
2
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
©
2017 Microchip Technology Inc.
Datasheet
DS40001816E-page 4
Debug(1)
I
I
I
I
I
EUSART
I/O Pins
I2C/SPI
Timer
CWG
SMT
PPS
Debug(1)
I
I
I
EUSART
I/O Pins
I2C/SPI
Timer
CWG
SMT
PPS
PIC18(L)F26/45/46K40
Peripheral Module Disable
Low Voltage Detect (LVD)
CRC with Memory Scan
Program Memory Flash
(bytes)
Temperature Indicator
Y
Y
Windowed Watchdog
8-bit TMR with HLT
Zero-Cross Detect
Computation (ch)
10-bit ADC2 with
CCP/10-bit PWM
Data EEPROM
(bytes)
Comparators
16-bit Timers
Data SRAM
(bytes)
5-bit DAC
Device
PIC18(L)F66K40
PIC18(L)F67K40
64k
128k
3562
3562
1024
1024
60
60
5
5
3
3
45
47
1
1
1
1
5/2
5/2
1
1
2
2
1
1
4
4
Y
Y
Y
Y
5
5
2
2
Y
Y
Y
Y
Note:
Debugging Methods: (I) – Integrated on Chip.
Data Sheet Index:
1.
2.
3.
4.
DS40001843 PIC18(L)F24/25K40 Data Sheet, 28-Pin, 8-bit Flash Microcontrollers
DS40001816 PIC18(L)F26/45/46K40 Data Sheet, 28/40/44-Pin, 8-bit Flash Microcontrollers
DS40001844 PIC18(L)F27/47K40 Data Sheet, 28/40/44-Pin, 8-bit Flash Microcontrollers
DS40001842 PIC18(L)F65/66K40 Data Sheet, 64-Pin, 8-bit Flash Microcontrollers
Sheet, 64-Pin, 8-bit Flash Microcontrollers
Pin Diagrams
Filename:
00-000028A.vsd
5.
Title:
DS40001841 PIC18(L)F67K40 Data
28-pin DIP
Last Edit:
3/6/2017
First Used:
N/A
Notes:
Generic 28-pin dual in-line diagram
Figure 1. 28-pin SPDIP, SSOP, SOIC
Rev. 00-000 028A
3/6/201 7
MCLR/V
PP
/RE3
RA0
RA1
RA2
RA3
RA4
RA5
V
SS
RA7
RA6
RC0
RC1
RC2
RC3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
RB7/ICSPDAT
RB6/ICSPCLK
RB6
RB4
RB3
RB2
RB1
RB0
V
DD
V
SS
RC7
RC6
RC5
RC4
©
2017 Microchip Technology Inc.
Datasheet
DS40001816E-page 5
Debug(1)
I
I
EUSART
I/O Pins
I2C/SPI
Timer
CWG
SMT
PPS
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