EEWORLDEEWORLDEEWORLD

Part Number

Search
 PDF

2220H5000360FQR

Description
Ceramic Capacitor, Multilayer, Ceramic, 500V, 1% +Tol, 1% -Tol, C0G, 30ppm/Cel TC, 0.000036uF, Surface Mount, 2220, CHIP
CategoryPassive components    capacitor   
File Size695KB,2 Pages
ManufacturerSyfer
Download Datasheet Parametric View All

2220H5000360FQR Overview

Ceramic Capacitor, Multilayer, Ceramic, 500V, 1% +Tol, 1% -Tol, C0G, 30ppm/Cel TC, 0.000036uF, Surface Mount, 2220, CHIP

2220H5000360FQR Parametric

Parameter NameAttribute value
Is it lead-free?Contains lead
Is it Rohs certified?incompatible
MakerSyfer
package instruction, 2220
Reach Compliance Codecompliant
ECCN codeEAR99
capacitance0.000036 µF
Capacitor typeCERAMIC CAPACITOR
dielectric materialsCERAMIC
high4.2 mm
JESD-609 codee0
length5.7 mm
Manufacturer's serial number2220
Installation featuresSURFACE MOUNT
multi-layerYes
negative tolerance1%
Number of terminals2
Maximum operating temperature125 °C
Minimum operating temperature-55 °C
Package shapeRECTANGULAR PACKAGE
Package formSMT
method of packingTR, 13 INCH
positive tolerance1%
Rated (DC) voltage (URdc)500 V
seriesSIZE(HIGH Q)
size code2220
surface mountYES
Temperature characteristic codeC0G
Temperature Coefficient-/+30ppm/Cel ppm/°C
Terminal surfaceTin/Lead (Sn90Pb10) - with Nickel (Ni) barrier
Terminal shapeWRAPAROUND
width5 mm
Modelsim Independent Simulation Tutorial
I. Simulation steps of GUI interface[/size][/font][/color][/align][align=left][color=rgb(51, 51, 51)][font=Avenir, "][size=14px] 1. First, put all the design text and simulation text you need to simul...
大辉哥0614 EE_FPGA Learning Park
CES Best Innovation Product Awards: 35 products unveiled (2)
[i=s]This post was last edited by jameswangsynnex on 2015-3-3 20:00[/i]...
aifang Mobile and portable
TMS320C55x DSP Library
The DSP Library (DSPLIB) is a collection of high-level optimized DSP function blocks for the C55x DSP platform. This source code library includes C call functions (compatible with the ANSI-C language)...
灞波儿奔 DSP and ARM Processors
USB interface reading and writing design based on FPGA.pdf
USB interface reading and writing design based on FPGA.pdf...
雷北城 EE_FPGA Learning Park
51 IO port simulation serial communication C source program
8){fontsize_6562.style.fontSize=(--curfontsize_6562)+"pt";fontsize_6562.style.lineHeight=(--curlineheight_6562)+"pt";}' Reduce font sizeIncrease font size#include reg51.h sbit BT_SND =P1^0; sbit BT_RE...
rain 51mcu
DSP system design issues
[size=4] DSP hardware design includes: hardware solution design, DSP and peripheral device selection, schematic design, PCB design and simulation, hardware debugging, etc. In the previous lecture, we ...
Aguilera DSP and ARM Processors

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2024 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号