Measured from the time ST pin crosses 50% threshold
Measured from the time VDD reaches 90% of its final value
-
1.3
2.5
ns
T_jitt
-
90
140
ps
f=6.144 MHz
f = 6.144 MHz, Integration bandwidth = 100 Hz to 40 kHz. Inclu-
sive of 50 mV peak-to-peak sinusoidal noise on V
DD
. Noise
frequency 100 Hz to 20 MHz.
SYMBOL
MIN.
TYP.
MAX.
UNIT
CONDITION
Notes:
1. Current consumption with load is a function of the output frequency and output load. For any given output frequency, the capacitive loading will increase current con-
sumption equal to C_load*VDD*f(MHz).
2. All Min and Max limits are specified over temperature and rated operating voltage with 15 pF output load unless otherwise stated. Typical values are at 25°C and nomi-
nal supply voltage.
PIN DESCRIPTION
Pin
1
2
3
4
Symbol
ST
OUT
V
DD
GND
I/O
Input
Output
Power
Power
Functionality
L: Specified frequency output
H: Output is low ( weak pull down). Device goes to the standby mode.
Supply current reduces to I_std.
LVCMOS clock output
Supply voltage. A capacitor value of 0.01 µF between VDD and GND is
recommended.
Connect to ground
[3]
Notes:
3. A capacitor of value 0.01µF between VDD and GND is required. (0.01µF X7R)
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