Memory Module Specifications
KVR1333D3E9SK2/16G
16GB (8GB 2Rx8 1G x 72-Bit x 2 pcs.)
PC3-10600 CL9 240-Pin ECC DIMM Kit
Important Information:
The module defined in this data sheet is one of several configurations available under
this part number. While all configurations are compatible, the DRAM combination and/or the module height may
vary from what is described here.
DESCRIPTION
ValueRAM's KVR1333D3E9SK2/16G is a kit of two 1G x 72-bit
(8GB) DDR3-1333 CL9 SDRAM (Synchronous DRAM), 2Rx8,
ECC memory modules, based on eighteen 512M x 8-bit FBGA
components per module. Total kit capacity is 16GB. The SPD's
are programmed to JEDEC standard latency DDR3-1333 timing
of 9-9-9 at 1.5V. Each 240-pin DIMM uses gold contact fingers.
The electrical and mechanical specifications are as follows:
SPECIFICATIONS
CL(IDD)
Row Cycle Time (tRCmin)
Refresh to Active/Refresh
Command Time (tRFCmin)
Row Active Time (tRASmin)
Power (Operating)
UL Rating
Operating Temperature
Storage Temperature
9 cycles
49.5ns (min.)
260ns (min.)
36ns (min.)
1.310 W* (per module)
94 V - 0
0
o
C to 85
o
C
-55
o
C to +100
o
C
FEATURES
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JEDEC standard 1.5V (1.425V ~1.575V) Power Supply
VDDQ = 1.5V (1.425V ~ 1.575V)
667MHz fCK for 1333Mb/sec/pin
8 independent internal bank
Programmable CAS Latency: 9, 8, 7, 6
Programmable Additive Latency: 0, CL - 2, or CL - 1 clock
Programmable CAS Write Latency(CWL) = 7 (DDR3-1333)
8-bit pre-fetch
Burst Length: 8 (Interleave without any limit, sequential with
starting address “000” only), 4 with tCCD = 4 which does not
allow seamless read or write [either on the fly using A12 or
MRS]
Bi-directional Differential Data Strobe
Thermal Sensor Grade B
Internal(self) calibration : Internal self calibration through ZQ
pin (RZQ : 240 ohm ± 1%)
On Die Termination using ODT pin
Average Refresh Period 7.8us at lower than TCASE 85°C,
3.9us at 85°C < TCASE < 95°C
Asynchronous Reset
PCB: Height 1.18” (30mm), double sided component
*Power will vary depending on the SDRAM used.
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Continued >>
Document No. VALUERAM1028-001.B00
10/10/14
Page 1
FPGA/CPLD
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