Preliminary Datasheet
μ
PD70F3826, 70F3827, 70F3828, 70F3829, 70F3830, 70F3831,
R01DS0029EJ0001
70F3832, 70F3833, 70F3834, 70F3835, 70F3836, 70F3837
Rev.0.01
−V850ES/JE3-E,
V850ES/JF3-E, V850ES/JG3-E− RENESAS MCU
Description
The
μ
PD70F3826, 70F3827, 70F3828, 70F3829 (V850ES/JF3-E), and
μ
PD70F3830, 70F3831, 70F3832, 70F3833
(V850ES/JF3-E), and
μ
PD70F3834, 70F3835, 70F3836, 70F3837 (V850ES/JG3-E) are products of the V850 32-bit
single-chip microcontrollers, and include peripheral functions such as ROM/RAM, timer/counters, serial interfaces, an
A/D converter, a DMA controller , a CAN controller , a USB function controller , and a Ethernet controller.
In addition to their high real-time responsiveness and one-clock-pitch execution of instructions, the V850ES/JE3-E,
V850ES/JF3-E, and V850ES/JG3-E include instructions executed via a hardware multiplier, saturation instructions, and
bit manipulation instructions.
Detailed function descriptions are provided in the following user’s manuals. Be sure to read them before
designing.
V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E Hardware User’s Manual: To be prepared
V850ES Architecture User’s Manual:
U15943E
Sep 30, 2010
Features
Number of instructions: 83
Minimum instruction execution time:
20 ns (@ 50 MHz operation with main clock (f
XX
))
Clock
•
Main clock oscillation: f
X
= 3 to 6.25 MHz
•
Subclock oscillation: f
XT
= 32.768 kHz
•
Internal oscillation: f
R
= 220 kHz (TYP.)
General-purpose registers: 32 bits
×
32 registers
Instruction set:
Signed multiplication, saturation operations, 32-bit
shift instructions, bit manipulation instructions,
load/store instructions
Memory space:
64 MB linear address space
Internal memory
Flash memory: 64/128/256 KB
RAM:
32/48/64 KB
(Including 16 KB of data RAM area)
I/O lines Total: 26/42/62
Interrupts and exceptions
Non-maskable interrupts: 2 sources
Maskable interrupts:
63/78/85 sources
Timer/counters
16-bit timer/event counter AA (TAA): 5 channels
16-bit timer/event counter AB (TAB): 1 channel
Motor control function supported
16-bit interval timer M (TMM):
4 channels
16-bit encoder timer T (TMT):
1 channel
Real-time counter: 1 channel
Watchdog timer: 1 channel
Real-time output function: 6 channels
A/D converter: 10-bit resolution
×
10/10 channels
Ethernet controller:
1 channel
USB function controller:
1 channel
Serial interface
•
CAN :1 channel (
μ
PD70F3829, 70F3833, 70F3837 only)
•
Asynchronous serial interface C(UARTC): 3/4 channels
•
Clocked serial interface F(CSIF):
2/3/5 channels
2
•
I C bus interface:
2/3 channels
DMA controller: 4 channels
Power save function:
HALT/IDLE1/IDLE2/STOP/subclock/sub-IDLE mode
On-chip debug function
Package: 64-pin LQFP (V850ES/JE3-E)
64-pin WQFN (V850ES/JE3-E)
80-pin LQFP (V850ES/JF3-E)
100-pin LQFP (V850ES/JG3-E)
113-pin FBGA (Under planing)
Operating supply voltage: 2.85 to 3.6 V
R01DS0029EJ0001 Rev.0.01
Sep 30, 2010
Page 1 of 75
μ
PD70F3826, 70F3827, 70F3828, 70F3829, 70F3830, 70F3831, 70F3832, 70F3833, 70F3834, 70F3835, 70F3836, 70F3837
Function list (V850ES/JE3-E)
Generic Name
Product Name
Internal
Flash memory
memory Internal RAM
Data RAM
Memory space
General-purpose register
Clocks
Main clock oscillation
Subclock oscillation
Internal oscillation
Minimum instruction
execution time
I/O ports
Timer
16-bit TAA
16-bit TAB
16-bit TMM
16-bit TMT
Motor control
Watch timer
WDT
Real-time output function
10-bit A/D converter
Serial
interface
CSIF/UARTC
CSIF/UARTC/I C
CSIF
UARTC/I C
UARTC/I C/CAN
USB function
Ethernet controller
DMA controller
Interrupt
source
External
Internal
Note 1, 2
2
2
2
V850ES/JE3-E
μ
PD70F3826
64 KB
16 KB
16 KB
64 MB
32 bits
×
32 registers
μ
PD70F3827
128 KB
32 KB
16 KB
μ
PD70F3828
256 KB
48 KB
16 KB
μ
PD70F3829
256 KB
48 KB
16 KB
PLL mode : f
X
= 3 to 6.25 MHz, f
XX
= 24 to 50 MHz (multiplication by 8)
Clock through mode : f
X
= 3 to 6.25 MHz ( internal : f
XX
= 3 to 6.25 MHz)
f
XT
= 32.768 kHz
f
R
= 220 kHz (TYP.)
20 ns (@ 50 MHz operation with main system clock (f
XX
))
I/O: 26 (5 V tolerant : 12)
5 channels (among which two channels have the interval function only)
−
4 channels
1 channel (Interval function only)
−
1 channel (RTC)
1 channel
6 bits
×
1 channel
10 channels
1 channel
1 channel
−
1 channel
−
1 channel
1 channel
4 channels (transfer target: on-chip peripheral I/O, internal RAM)
7(7)
54
7(7)
54
7(7)
54
7(7)
58
1 channel
−
Power-save function
Reset factor
On-chip debugging
Operating supply voltage
Operating ambient temperature
Package
HALT/IDLE1/IDLE2/STOP/subclock/sub-IDLE modes
RESET pin input, watchdog timer 2 (WDT2), clock monitor (CLM), low-voltage detector (LVI)
MINICUBE , MINICUBE2 supported
2.85 to 3.6 V
−40
to +85°C
64-pin plastic LQFP (fine pitch) (10
×
10 mm), 64-pin plastic WQFN (9
×
9 mm),
®
Notes 1.
The figure in parentheses indicates the number of external interrupts that can release the STOP mode.
Notes
2.
Include NMI.
R01DS0029EJ0001 Rev.0.01
Sep 30, 2010
Page 2 of 75
μ
PD70F3826, 70F3827, 70F3828, 70F3829, 70F3830, 70F3831, 70F3832, 70F3833, 70F3834, 70F3835, 70F3836, 70F3837
Function list (V850ES/JF3-E)
Generic Name
Product Name
Internal
Flash memory
memory Internal RAM
Data RAM
Memory space
General-purpose register
Clocks
Main clock oscillation
Subclock oscillation
Internal oscillation
Minimum instruction
execution time
I/O ports
Timer
16-bit TAA
16-bit TAB
16-bit TMM
16-bit TMT
Motor control
Watch timer
WDT
Real-time output function
10-bit A/D converter
Serial
interface
CSIF/UARTC
CSIF/UARTC/I C
CSIF
UARTC/I C
UARTC/I C/CAN
USB function
Ethernet controller
DMA controller
Interrupt
source
External
Internal
Note 1, 2
2
2
2
V850ES/JF3-E
μ
PD70F3830
64 KB
16 KB
16 KB
64 MB
32 bits
×
32 registers
μ
PD70F3831
128 KB
32 KB
16 KB
μ
PD70F3832
256 KB
48 KB
16 KB
μ
PD70F3833
256 KB
48 KB
16 KB
PLL mode : f
X
= 3 to 6.25 MHz, f
XX
= 24 to 50 MHz (multiplication by 8)
Clock through mode : f
X
= 3 to 6.25 MHz ( internal : f
XX
= 3 to 6.25 MHz)
f
XT
= 32.768 kHz
f
R
= 220 kHz (TYP.)
20 ns (@ 50 MHz operation with main system clock (f
XX
))
I/O: 42 (5 V tolerant : 28)
5 channels
1 channel
4 channels
1 channel
1 channel
1 channel (RTC)
1 channel
6 bits
×
1 channel
10 channels
1 channel
2 channels
−
1 channel
−
1 channel
1 channel
4 channels (transfer target: on-chip peripheral I/O, internal RAM)
19(19)
57
19(19)
57
19(19)
57
19(19)
61
1 channel
−
Power-save function
Reset factor
On-chip debugging
Operating supply voltage
Operating ambient temperature
Package
HALT/IDLE1/IDLE2/STOP/subclock/sub-IDLE modes
RESET pin input, watchdog timer 2 (WDT2), clock monitor (CLM), low-voltage detector (LVI)
MINICUBE, MINICUBE2 supported
2.85 to 3.6 V
−40
to +85°C
80-pin plastic LQFP (fine pitch) (12
×
12 mm)
Notes 1.
The figure in parentheses indicates the number of external interrupts that can release the STOP mode.
Notes
2.
Include NMI.
R01DS0029EJ0001 Rev.0.01
Sep 30, 2010
Page 3 of 75
μ
PD70F3826, 70F3827, 70F3828, 70F3829, 70F3830, 70F3831, 70F3832, 70F3833, 70F3834, 70F3835, 70F3836, 70F3837
Function list (V850ES/JG3-E)
Generic Name
Product Name
Internal
Flash memory
memory Internal RAM
Data RAM
Memory space
General-purpose register
Clocks
Main clock oscillation
Subclock oscillation
Internal oscillation
Minimum instruction
execution time
I/O ports
Timer
16-bit TAA
16-bit TAB
16-bit TMM
16-bit TMT
Motor control
Watch timer
WDT
Real-time output function
10-bit A/D converter
Serial
interface
CSIF/UARTC
CSIF/UARTC/I C
CSIF
UARTC/I C
UARTC/I C/CAN
USB function
Ethernet controller
DMA controller
Interrupt
source
External
Internal
Note 1, 2
2
2
2
V850ES/JG3-E
μ
PD70F3834
64 KB
16 KB
16 KB
64 MB
32 bits
×
32 registers
μ
PD70F3835
128 KB
32 KB
16 KB
μ
PD70F3836
256 KB
48 KB
16 KB
μ
PD70F3837
256 KB
48 KB
16 KB
PLL mode : f
X
= 3 to 6.25 MHz, f
XX
= 24 to 50 MHz (multiplication by 8)
Clock through mode : f
X
= 3 to 6.25 MHz ( internal : f
XX
= 3 to 6.25 MHz)
f
XT
= 32.768 kHz
f
R
= 220 kHz (TYP.)
20 ns (@ 50 MHz operation with main system clock (f
XX
))
I/O: 62 (5 V tolerant : 35)
5 channels
1 channel
4 channels
1 channel
1 channel
1 channel (RTC)
1 channel
6 bits
×
1 channel
10 channels
1 channel
2 channels
2 channels
1 channel
−
1 channel
1 channel
4 channels (transfer target: on-chip peripheral I/O, internal RAM)
22(22)
61
22(22)
61
22(22)
61
22(22)
65
1 channel
−
Power-save function
Reset factor
On-chip debugging
Operating supply voltage
Operating ambient temperature
Package
HALT/IDLE1/IDLE2/STOP/subclock/sub-IDLE modes
RESET pin input, watchdog timer 2 (WDT2), clock monitor (CLM), low-voltage detector (LVI)
MINICUBE, MINICUBE2 supported
2.85 to 3.6 V
−40
to +85°C
100-pin plastic LQFP (fine pitch) (14
×
14 mm), 113-pin plastic FBGA
Note3
Notes 1.
The figure in parentheses indicates the number of external interrupts that can release the STOP mode.
Notes
2.
Include NMI.
3.
Under planning.
R01DS0029EJ0001 Rev.0.01
Sep 30, 2010
Page 4 of 75
μ
PD70F3826, 70F3827, 70F3828, 70F3829, 70F3830, 70F3831, 70F3832, 70F3833, 70F3834, 70F3835, 70F3836, 70F3837
APPLICATIONS
Applications that require Ethernet controller
Home audio, printers, and scanners.
ORDERING INFORMATION
•
V850ES/JE3-E
Part Number
Package
64-pin plastic LQFP (fine pitch) (10
×
10)
64-pin plastic LQFP (fine pitch) (10
×
10)
64-pin plastic LQFP (fine pitch) (10
×
10)
64-pin plastic LQFP (fine pitch) (10
×
10)
64-pin plastic WQFN (9
×
9)
64-pin plastic WQFN (9
×
9)
64-pin plastic WQFN (9
×
9)
64-pin plastic WQFN (9
×
9)
On-Chip Flash Memory
64 KB
128 KB
256 KB
256 KB
64 KB
128 KB
256 KB
256 KB
μ
PD70F3826GB-GAH-AX
μ
PD70F3827GB-GAH-AX
μ
PD70F3828GB-GAH-AX
μ
PD70F3829GB-GAH-AX
μ
PD70F3826K8-6B4-AX
μ
PD70F3827K8-6B4-AX
μ
PD70F3828K8-6B4-AX
μ
PD70F3829K8-6B4-AX
•
V850ES/JF3-E
Part Number
Package
80-pin plastic LQFP (fine pitch) (12
×
12)
80-pin plastic LQFP (fine pitch) (12
×
12)
80-pin plastic LQFP (fine pitch) (12
×
12)
80-pin plastic LQFP (fine pitch) (12
×
12)
On-Chip Flash Memory
64 KB
128 KB
256 KB
256 KB
μ
PD70F3830GK-GAK-AX
μ
PD70F3831GK-GAK-AX
μ
PD70F3832GK-GAK-AX
μ
PD70F3833GK-GAK-AX
•
V850ES/JG3-E
Part Number
Package
100-pin plastic LQFP (fine pitch) (14
×
14)
100-pin plastic LQFP (fine pitch) (14
×
14)
100-pin plastic LQFP (fine pitch) (14
×
14)
100-pin plastic LQFP (fine pitch) (14
×
14)
113-pin plastic FBGA (8
×
8)
On-Chip Flash Memory
64 KB
128 KB
256 KB
256 KB
256 KB
μ
PD70F3834GC-UEU-AX
μ
PD70F3835GC-UEU-AX
μ
PD70F3836GC-UEU-AX
μ
PD70F3837GC-UEU-AX
μ
PD70F3837F1-CAH-AX
Note
Note
Remark
Under planning
The V850ES/Jx3-E microcontrollers are lead-free products.
R01DS0029EJ0001 Rev.0.01
Sep 30, 2010
Page 5 of 75
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