DATASHEET
ISL6548A
ACPI Regulator/Controller for Dual Channel DDR Memory Systems
The ISL6548A provides a complete ACPI compliant power
solution for up to 4 DIMM dual channel DDR/DDR2 Memory
systems. Included are both a synchronous buck controller to
supply V
DDQ
during S0/S1 and S3 states. During S0/S1
state, a fully integrated sink-source regulator generates an
accurate (V
DDQ
/2) high current V
TT
voltage without the
need for a negative supply. A second PWM controller, which
requires external MOSFET drivers, is available for regulation
of the GMCH Core voltage. A sink/source LDO controller is
also integrated for the CPU/GMCH V
TT
termination voltage
regulation. Another LDO is available for the ICH7 voltage.
The switching PWM controller drives two N-Channel
MOSFETs in a synchronous-rectified buck converter
topology. The synchronous buck converter uses voltage-
mode control with fast transient response. The switching
regulator provides a maximum static regulation tolerance of
2% over line, load, and temperature ranges. The output is
user-adjustable by means of external resistors down to 0.8V.
An integrated soft-start feature brings all outputs into
regulation in a controlled manner when returning to S0/S1
state from any sleep state. During S0 the VIDPGD signal
indicates that the GMCH and CPU V
TT
termination voltage
is within spec and operational.
All outputs, except V
ICH7
, have undervoltage protection. The
switching regulator also has overvoltage and overcurrent
protection. Thermal shutdown is integrated.
FN9189
Rev 2.00
January 3, 2006
Features
• Generates 5 Regulated Voltages
- Synchronous Buck PWM Controller for DDR V
DDQ
- 3A Integrated Sink/Source Linear Regulator with
Accurate V
DDQ
/2 Divider Reference for DDR V
TT
- PWM Regulator for GMCH Core
- Sink/Source LDO Regulator for CPU/GMCH V
TT
Termination
- LDO Regulator for ICH7
• ACPI Compliant Sleep State Control
• Glitch-free Transitions During State Changes
• V
DDQ
PWM Controller Drives Low Cost N-Channel
MOSFETs
• 250kHz Constant Frequency Operation
- Both PWM Controllers are Phase Shifted 180°
• Tight Output Voltage Regulation
- All Outputs:
2% Over Temperature
• Fully-Adjustable Outputs with Wide Voltage Range: Down
to 0.8V supports DDR and DDR2 Specifications
• Simple Single-Loop Voltage-Mode PWM Control Design
• Fast PWM Converter Transient Response
• Under and Overvoltage Monitoring
• OCP on the V
DDQ
Switching Regulator
• Integrated Thermal Shutdown Protection
• Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
• Single and Dual Channel DDR Memory Power Systems in
ACPI Compliant PCs
• Graphics Cards - GPU and Memory Supplies
• ASIC Power Supplies
• Embedded Processor and I/O Supplies
• DSP Supplies
FN9189 Rev 2.00
January 3, 2006
Page 1 of 16
ISL6548A
Ordering Information
PART
NUMBER
ISL6548ACRZA
(Note)
PART
MARKING
ISL6548ACRZ
TEMP.
RANGE
(°C)
0 to 70
0 to 70
PACKAGE
PKG.
DWG. #
Pinout
ISL6548A (QFN)
TOP VIEW
OCSET
22
21
20
19
GND
29
18
17
16
15
8
VDDQ
9
DDR_VTTSNS
10
DRIVE2_U
11
FB2
12
VIDPGD
13
DRIVE2_L
14
VREF_IN
DRIVE3
FB3
PWM4
FB4
COMP4
COMP
FB
PHASE
24
UGATE
LGATE
BOOT
GND
28 Ld 6x6 QFN L28.6x6
(Pb-free)
28 Ld 6x6 QFN L28.6x6
(Pb-free)
Tape and Reel
5VSBY
S3#
P12V
GND
DDR_VTT
DDR_VTT
VDDQ
1
2
3
4
5
6
7
28
27
26
25
ISL6548ACRZA-T ISL6548ACRZ
(Note)
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100% matte
tin plate termination finish, which are RoHS compliant and compatible
with both SnPb and Pb-free soldering operations. Intersil Pb-free
products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
FN9189 Rev 2.00
January 3, 2006
S5#
23
Page 2 of 16
FN9189 Rev 2.00
January 3, 2006
Page 3 of 16
Block Diagram
ISL6548A
5VSBY
P12V
S3#
S5#
FB
COMP
180°
PWM4
PHASE
SHIFT
250kHz
OSCILLATOR
EA1
POR
PWM
EA1 ACTIVE
IN S3
MONITOR AND CONTROL
5VSBY
BOOT
UGATE
COMP4
EA4
LGATE
FB4
P12V
EA2
DRIVE2_U
FB2
SOFT-START & ENABLE A
SOFT-START & ENABLE B
SOFT-START & ENABLE C
ENABLE DDR_VTT
ENABLE VIDPGD
VOLTAGE
REFERENCE
0.800V
0.680V (-15%)
0.920V (+15%)
FAULT
OC
COMP
PHASE
OCSET
20A
VTTSNS
S3
VDDQ(2)
VTT(2)
R
U
DRIVE2_L
UV
UV/OV
P12V
EA3
DRIVE3
FB3
UV
VTT
REG
UV/OV
VREF_IN
R
L
VIDPGD
GND PAD
GND(2)
ISL6548A
Simplified Power System Diagram
5VSBY
12V
5VDUAL
3V3ATX
SLP_S3
SLP_S5
SLEEP
STATE
LOGIC
ISL6548A
Q1
PWM
CONTROLLER
V
DDQ
Q2
+
V
GMCH
+
Q3
Intersil
FET DRIVER
PWM
CONTROLLER
Q4
V
REF
VTT
REGULATOR
Q5
V
TT_GMCH/CPU
+
Q6
LINEAR
CONTROLLER
LINEAR
CONTROLLER
+
3V3ATX or V
GMCH
Q7
V
ICH7
+
V
TT
Typical Application
5VSBY
3VDUAL
5VDUAL
12V
D
BOOT
5VSBY
VIDPGD
ATX3V3
SLP_S5
SLP_S3
Intersil
FET DRIVER
S5#
S3#
P12V
BOOT
R
OCSET
OCSET
C
BOOT
V
GMCH
Q3
ISL6548A
PWM4
UGATE
PHASE
Q1
V
DDQ_DDR
+
Q4
LGATE
R6
COMP4
DDR_VDDQ(x2)
COMP
FB4
R2
FB
DRIVE2_U
FB2
VREF_IN
R4
C1
C2
Q2
C5
C6
R5
R8
C7
V
TT_GMCH/CPU
Q5
R7
R3
C3
R1
R9
DDR_VTT(x2)
ATX3V3 or V
GMCH
DDR_VTTSNS
V
TT_DDR
R10
Q6
DRIVE2_L
GND
DRIVE3
FB3
R12
R11
Q7
V
ICH7
FN9189 Rev 2.00
January 3, 2006
Page 4 of 16
ISL6548A
Absolute Maximum Ratings
5VSBY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to +7V
P12V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to +14V
Absolute Boot Voltage, V
BOOT
. . . . . . . . . . . . . . . . . . . . . . . +15.0V
Upper Driver Supply Voltage, V
BOOT
- V
PHASE
. . . . . . . . . . . +6.0V
All other Pins . . . . . . . . . . . . . . . . . . . . GND - 0.3V to 5VCC + 0.3V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 2
Thermal Information
Thermal Resistance (Typical, Notes 1, 2)
JA
(°C/W)
JC
(°C/W)
QFN Package . . . . . . . . . . . . . . . . . . .
32
4
Maximum Junction Temperature (Plastic Package) . . . . . . . . 150°C
Maximum Storage Temperature Range . . . . . . . . . . . -65°C to 150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300°C
Recommended Operating Conditions
Supply Voltage on 5VSBY . . . . . . . . . . . . . . . . . . . . . . . . +5V ±10%
Supply Voltage on P12V . . . . . . . . . . . . . . . . . . . . . . . . +12V ±10%
Ambient Temperature Range . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Junction Temperature Range. . . . . . . . . . . . . . . . . . . . 0°C to 125°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1.
JA
is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379.
2. For
JC
, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications
PARAMETER
5VSBY SUPPLY CURRENT
Nominal Supply Current
Recommended Operating Conditions, Unless Otherwise Noted. Refer to Block and Simplified Power System
Diagrams and Typical Application Schematics
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
I
CC_S0
I
CC_S5
S3# & S5# HIGH, UGATE/LGATE Open
S5# LOW, S3# Don’t Care, UGATE/LGATE Open
5.5
-
7.0
700
8.0
850
mA
A
POWER-ON RESET
Rising 5VSBY POR Threshold
Falling 5VSBY POR Threshold
Rising P12V POR Threshold
Falling P12V POR Threshold
OSCILLATOR AND SOFT-START
PWM Frequency
Ramp Amplitude
Soft-Start Interval
REFERENCE VOLTAGE
Reference Voltage
System Accuracy
V
DDQ
AND V
GMCH
PWM CONTROLLER ERROR AMPLIFIERS
DC Gain
Gain-Bandwidth Product
Slew Rate
CONTROL I/O (S3#, S5#)
LOW Level Input Threshold
HIGH Level Input Threshold
0.75
-
-
-
-
2.2
V
V
GBWP
SR
Guaranteed By Design
-
15
-
80
-
6
-
-
-
dB
MHz
V/s
V
REF
-
-2.0
0.800
-
-
+2.0
V
%
f
OSC
V
OSC
t
SS
220
-
6.5
250
1.5
8.2
280
-
9.5
kHz
V
ms
4.10
3.60
10.0
8.80
-
-
-
-
4.45
3.95
10.5
9.75
V
V
V
V
FN9189 Rev 2.00
January 3, 2006
Page 5 of 16
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