AS5SS128K36DQ-7.5L/IT datasheet, PDF

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AS5SS128K36DQ-7.5L/IT: DescriptionStandard SRAM; Categorystorage storage; File Size348KB，20 Pages; ManufacturerMicross; Websitehttps://www.micross.com

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AS5SS128K36DQ-7.5L/IT Overview

Standard SRAM

AS5SS128K36DQ-7.5L/IT Parametric

Parameter Name	Attribute value
Maker	Micross
package instruction	,
Reach Compliance Code	compliant
Memory IC Type	STANDARD SRAM

AS5SS128K36DQ-7.5L/IT Preview

SSRAM

AS5SS128K36

128K x 36 4Mb FLOW THROUGH ‘NO WAIT’

STATE BUS SYNCHRONOUS SRAM

FEATURES

• Available in Mil-Temp*, Enhanced* & Industrial Ranges

• 100 percent bus utilization

• No wait cycles between Read and Write

• Internal self-timed write cycle

• Individual Byte Write Control

• Single Read / Write control pin

• Clock controlled, registered address, data and

control

• Interleaved or linear burst sequence control using

MODE input

• Three chip enables for simple depth expansion

and address pipelining

• Power down mode

• Common data inputs and data outputs

• CKE\ pin to enable clock and suspend operation

• Power Supply: V

3.3V ± 5%, V

DDQ

3.3V/2.5V ± 5%

• JEDEC 100-Pin TQFP

• TQFP in copper lead frame for superior thermal

performance

• RoHs compliant options available

*Consult factory for /XT and /ET products.

GENERAL DESCRIPTION

TheAS5SS128K36 is a high-speed, low-power synchronous

static RAM designed to provide a burstable, high-performance,

“no wait” state device for networking and communication ap-

plications. It is organized as 128K words by 36 bits fabricated

with Micross’ advanced CMOS technology.

Incorporating a ‘no wait’ state feature, wait cycles are eliminated

when the bus switches from read to write, or write to read.

This device integrates a 2-bit burst counter, high-speed SRAM

core, and high-drive capability outputs into a single monolithic

circuit.

All synchronous inputs pass through registers are controlled by

a positive-edge-triggered single clock input. Operations may

be suspended and all synchronous inputs ignored when Clock

Enable, CKE\ is HIGH. In this state the internal device will hold

their previous values.

All Read, Write and Deselect cycles are initiated by the ADV

input. When the ADV is HIGH the internal burst counter is

incremented. New external addresses can be loaded when

ADV is LOW.

Write cycles are internally self-timed and are initiated by the

rising edge of the clock inputs and when WE\ is LOW. Separate

byte enables allow individual bytes to be written. A burst mode

pin (MODE) deﬁnes the order of the burst sequence. When tied

HIGH, the interleaved burst sequence is selected. When tied

LOW, the linear burst sequence is selected.

FAST ACCESS TIME

Symbol

MAX

Parameter

Clock Access Time

Cycle Time

Frequency

7.5

8.5

117

8.5

8.0

100

Units

MHz

NOTE 1:

Otherwise known as (ZBL) Zero Bus Latency.

For more products and information

please visit our web site at

www.micross.com

AS5SS128K36

Rev. 2.8 09/11

Micross Components reserves the right to change products or speciﬁcations without notice.

SSRAM

AS5SS128K36

BLOCK DIAGRAM

AS5SS128K36

Rev. 2.8 09/11

Micross Components reserves the right to change products or speciﬁcations without notice.

SSRAM

AS5SS128K36

PIN CONFIGURATIONS

100-pin TQFP

BWd

BWc

BWb

BWa

CKE

ADV

CE2

Vss

CLK

DQPc

DQc

DDQ

Vss

DQc

Vss

DDQ

DQc

Vss

DQd

DDQ

Vss

DQd

Vss

DDQ

DQd

DQPd

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

MODE

Vss

DQPb

DQb

DDQ

Vss

DQb

Vss

DDQ

DQb

Vss

DQa

DDQ

Vss

DQa

Vss

DDQ

DQa

DQPa

Synchronous Address Inputs. These

pins must tied to the two LSBs of the

address bus.

Synchronous Address Inputs.

CLK

Synchronous Clock

ADV

Synchronous Burst Address Advance

BWa\ , BWd\ Synchronous Byte Write Enable

WE\

Write Enable

A0, A1

CKE\

Clock Enable

Ground

Not Connetcted

CE\, CE2, CE2\ Synchronous Chip Enable

OE\

DQa DQd

DQPa DQPd

MODE

DDQ

Output Enable

Synchronous Data Input / Output

Parity Data I/O

Burst Sequence Mode Selection

+3.3V / 2.5V Power Supply

Ground

Isolated Output Buffer Supply: 3.3V/2.5V

Snooze Enable

AS5SS128K36

Rev. 2.8 09/11

Micross Components reserves the right to change products or speciﬁcations without notice.

SSRAM

AS5SS128K36

STATE DIAGRAM

READ

BEGIN

READ

WRITE

READ

WRITE

BEGIN

WRITE

READ

WRITE

READ

BURST

DESELECT

BURST

WRITE

BURST

READ

WRITE

BURST

WRITE

BURST

READ

SYNCHRONOUS TRUTH TABLE

Operation

Not Selected

Not Selected Continue

Begin Burst Read

Continue Burst Read

NOP/Dummy Read

Dummy Read

Begin Burst Write

Continue Burst Write

NOP/Write Abort

Write Abort

Ignore Clock

Address Used

N/A

External Address

Next Address

External Address

Next Address

External Address

Next Address

N/A

Next Address

Current Address

OE\

CE2

CE2\

ADV

WE\

BWx\

OE\

CKE\

CLK

Notes:

1. X means “Don’t Care.”

2. The rising edge of clock is symbolized by .

3. A continue deselect cycle can only be entered if a deselected cycle is excecuted first.

4. WE\ = L means write operation in write truth table. WE\=H meansread operation in write truth table.

5. Operation finally depends on status of asynchronous pins (ZZ and OE\)

AS5SS128K36

Rev. 2.8 09/11

Micross Components reserves the right to change products or speciﬁcations without notice.

SSRAM

AS5SS128K36

ASYNCHRONOUS TRUTH TABLE

Function

Sleep Mode

Read

Write

Deselected

Notes:

1. X means “Don’t Care.”

2. For write cycles following read cycles, the output buffers must be disabled with OE\, otherwise data bus contention will occur.

3. Sleep Mode means power Sleep Mode where stand by current does not depend on cycle time.

4. Deselected means power Sleep Mode where stand by currend depends on cycle time.

OE\

I/O Status

High Z

Din, High Z

High Z

WRITE TRUTH TABLE

Operation

Read

WRITE BYTE a

WRITE BYTE b

WRITE BYTE c

WRITE BYTE d

WRITE ALL BYTEs

WRITE ABORT / NOP

WE\

Bwa\

BWb\

BWc\

BWd\

Notes:

1. X means “Don’t Care.”

2. All inputs in this table must beet setup and hold time around the rising edge of CLK.

INTERLEAVED BURST ADDRESS TABLE (MODE = V

or NC)

External Address

A1 A0

1st Burst Address

A1 A0

2nd Burst Address

A1 A0

3rd Burst Address

A1 A0

AS5SS128K36

Rev. 2.8 09/11

Micross Components reserves the right to change products or speciﬁcations without notice.

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AS5SS128K36DQ-7.5L/IT Related Products

	AS5SS128K36DQ-7.5L/IT	AS5SS128K36DQCR-8L/XT	AS5SS128K36DQ-7.5/XT	AS5SS128K36DQ-8/IT	AS5SS128K36DQ-7.5/IT	AS5SS128K36DQ-8/ET	AS5SS128K36DQ-7.5L/ET	AS5SS128K36DQ-7.5L/XT	AS5SS128K36DQ-8/XT	AS5SS128K36DQC-7.5L/IT
Description	Standard SRAM	Standard SRAM	Standard SRAM	Standard SRAM	Standard SRAM	Standard SRAM	Standard SRAM	Standard SRAM	Standard SRAM	Standard SRAM
Maker	Micross	Micross	Micross	Micross	Micross	Micross	Micross	Micross	Micross	Micross
Reach Compliance Code	compliant	compliant	compliant	compliant	compliant	compliant	compliant	compliant	compliant	compli
Memory IC Type	STANDARD SRAM	STANDARD SRAM	STANDARD SRAM	STANDARD SRAM	STANDARD SRAM	STANDARD SRAM	STANDARD SRAM	STANDARD SRAM	STANDARD SRAM	STANDARD SRAM

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Shortcut: 00 01 02 03 04 05 06 07 08 09 0A 0C 0F 0J 0L 0M 0R 0S 0T 0Z 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 1H 1K 1M 1N 1P 1S 1T 1V 1X 1Z 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 2G 2K 2M 2N 2P 2Q 2R 2S 2T 2W 2Z 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 3G 3H 3J 3K 3L 3M 3N 3P 3R 3S 3T 3V 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4M 4N 4P 4S 4T 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5E 5G 5H 5K 5M 5N 5P 5S 5T 5V 60 61 62 63 64 65 66 67 68 69 6A 6C 6E 6F 6M 6N 6P 6R 6S 6T 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7M 7N 7P 7Q 7V 7W 7X 80 81 82 83 84 85 86 87 88 89 8A 8D 8E 8L 8N 8P 8S 8T 8W 8Y 8Z 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9F 9G 9H 9L 9S 9T 9W

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