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Datasheet> All Categories > storage> storage> AS5SS128K36DQ-7.5L/XT
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AS5SS128K36DQ-7.5L/XT

Description
Standard SRAM
Categorystorage    storage   
File Size348KB，20 Pages
ManufacturerMicross
Websitehttps://www.micross.com
Download Datasheet Parametric Compare View All

AS5SS128K36DQ-7.5L/XT Overview

Standard SRAM

AS5SS128K36DQ-7.5L/XT Parametric

Parameter NameAttribute value
MakerMicross
package instruction,
Reach Compliance Codecompliant
Memory IC TypeSTANDARD SRAM

AS5SS128K36DQ-7.5L/XT Preview

SSRAM
AS5SS128K36
128K x 36 4Mb FLOW THROUGH ‘NO WAIT’
STATE BUS SYNCHRONOUS SRAM
FEATURES
• Available in Mil-Temp*, Enhanced* & Industrial Ranges
• 100 percent bus utilization
• No wait cycles between Read and Write
1
• Internal self-timed write cycle
• Individual Byte Write Control
• Single Read / Write control pin
• Clock controlled, registered address, data and
control
• Interleaved or linear burst sequence control using
MODE input
• Three chip enables for simple depth expansion
and address pipelining
• Power down mode
• Common data inputs and data outputs
• CKE\ pin to enable clock and suspend operation
• Power Supply: V
DD
3.3V ± 5%, V
DDQ
3.3V/2.5V ± 5%
• JEDEC 100-Pin TQFP
• TQFP in copper lead frame for superior thermal
performance
• RoHs compliant options available
*Consult factory for /XT and /ET products.
GENERAL DESCRIPTION
TheAS5SS128K36 is a high-speed, low-power synchronous
static RAM designed to provide a burstable, high-performance,
“no wait” state device for networking and communication ap-
plications. It is organized as 128K words by 36 bits fabricated
with Micross’ advanced CMOS technology.
Incorporating a ‘no wait’ state feature, wait cycles are eliminated
when the bus switches from read to write, or write to read.
This device integrates a 2-bit burst counter, high-speed SRAM
core, and high-drive capability outputs into a single monolithic
circuit.
All synchronous inputs pass through registers are controlled by
a positive-edge-triggered single clock input. Operations may
be suspended and all synchronous inputs ignored when Clock
Enable, CKE\ is HIGH. In this state the internal device will hold
their previous values.
All Read, Write and Deselect cycles are initiated by the ADV
input. When the ADV is HIGH the internal burst counter is
incremented. New external addresses can be loaded when
ADV is LOW.
Write cycles are internally self-timed and are initiated by the
rising edge of the clock inputs and when WE\ is LOW. Separate
byte enables allow individual bytes to be written. A burst mode
pin (MODE) defines the order of the burst sequence. When tied
HIGH, the interleaved burst sequence is selected. When tied
LOW, the linear burst sequence is selected.
FAST ACCESS TIME
Symbol
t
KQ
t
KC
f
MAX
Parameter
Clock Access Time
Cycle Time
Frequency
7.5
7.5
8.5
117
8.5
8.0
10
100
Units
ns
ns
MHz
NOTE 1:
Otherwise known as (ZBL) Zero Bus Latency.
For more products and information
please visit our web site at
www.micross.com
AS5SS128K36
Rev. 2.8 09/11
Micross Components reserves the right to change products or specifications without notice.
1
SSRAM
AS5SS128K36
BLOCK DIAGRAM
AS5SS128K36
Rev. 2.8 09/11
Micross Components reserves the right to change products or specifications without notice.
2
SSRAM
AS5SS128K36
PIN CONFIGURATIONS
100-pin TQFP
BWd
BWc
BWb
BWa
CKE
OE
ADV
NC
CE2
CE2
V
DD
Vss
CLK
WE
NC
CE
A
A
DQPc
DQc
DQc
V
DDQ
Vss
DQc
DQc
DQc
DQc
Vss
V
DDQ
DQc
DQc
NC
V
DD
NC
Vss
DQd
DQd
V
DDQ
Vss
DQd
DQd
DQd
DQd
Vss
V
DDQ
DQd
DQd
DQPd
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
80
1
79
2
78
3
77
4
76
5
75
6
74
7
73
8
72
9
71
10
70
11
69
12
68
13
67
14
66
15
65
16
64
17
63
18
62
19
61
20
60
21
59
22
58
23
57
24
56
25
55
26
54
27
53
28
52
29
51
30
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
MODE
A
A
A
A
NC
NC
Vss
A1
A0
NC
NC
A
A
A
A
A
V
DD
A
A
A
A
DQPb
DQb
DQb
V
DDQ
Vss
DQb
DQb
DQb
DQb
Vss
V
DDQ
DQb
DQb
Vss
NC
V
DD
ZZ
DQa
DQa
V
DDQ
Vss
DQa
DQa
DQa
DQa
Vss
V
DDQ
DQa
DQa
DQPa
Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
A
Synchronous Address Inputs.
CLK
Synchronous Clock
ADV
Synchronous Burst Address Advance
BWa\ , BWd\ Synchronous Byte Write Enable
WE\
Write Enable
A0, A1
CKE\
V
SS
NC
Clock Enable
Ground
Not Connetcted
CE\, CE2, CE2\ Synchronous Chip Enable
OE\
DQa DQd
DQPa DQPd
MODE
V
DD
V
SS
V
DDQ
ZZ
Output Enable
Synchronous Data Input / Output
Parity Data I/O
Burst Sequence Mode Selection
+3.3V / 2.5V Power Supply
Ground
Isolated Output Buffer Supply: 3.3V/2.5V
Snooze Enable
AS5SS128K36
Rev. 2.8 09/11
Micross Components reserves the right to change products or specifications without notice.
3
SSRAM
AS5SS128K36
STATE DIAGRAM
READ
BEGIN
READ
WRITE
DS
READ
DS
WRITE
BEGIN
WRITE
READ
WRITE
READ
BURST
DS
DESELECT
BURST
BURST
WRITE
DS
BURST
READ
WRITE
DS
BURST
WRITE
BURST
BURST
READ
SYNCHRONOUS TRUTH TABLE
1
Operation
Not Selected
Not Selected
Not Selected
Not Selected Continue
Begin Burst Read
Continue Burst Read
NOP/Dummy Read
Dummy Read
Begin Burst Write
Continue Burst Write
NOP/Write Abort
Write Abort
Ignore Clock
Address Used
N/A
N/A
N/A
N/A
External Address
Next Address
External Address
Next Address
External Address
Next Address
N/A
Next Address
Current Address
OE\
H
X
X
X
L
X
L
X
L
X
L
X
X
CE2
X
H
X
X
H
X
H
X
H
X
H
X
X
CE2\
X
X
H
X
L
X
L
X
L
X
L
X
X
ADV
L
L
L
H
L
H
L
H
L
H
L
H
X
WE\
X
X
X
X
H
X
H
X
L
X
L
X
X
BWx\
X
X
X
X
X
X
X
X
L
L
H
H
X
OE\
X
X
X
X
L
L
H
H
X
X
X
X
X
CKE\
L
L
L
L
L
L
L
L
L
L
L
L
H
CLK
Notes:
1. X means “Don’t Care.”
2. The rising edge of clock is symbolized by .
3. A continue deselect cycle can only be entered if a deselected cycle is excecuted first.
4. WE\ = L means write operation in write truth table. WE\=H meansread operation in write truth table.
5. Operation finally depends on status of asynchronous pins (ZZ and OE\)
AS5SS128K36
Rev. 2.8 09/11
Micross Components reserves the right to change products or specifications without notice.
4
SSRAM
AS5SS128K36
ASYNCHRONOUS TRUTH TABLE
1
Function
Sleep Mode
Read
Write
Deselected
Notes:
1. X means “Don’t Care.”
2. For write cycles following read cycles, the output buffers must be disabled with OE\, otherwise data bus contention will occur.
3. Sleep Mode means power Sleep Mode where stand by current does not depend on cycle time.
4. Deselected means power Sleep Mode where stand by currend depends on cycle time.
ZZ
H
L
L
L
L
OE\
X
L
H
X
X
I/O Status
High Z
DQ
High Z
Din, High Z
High Z
WRITE TRUTH TABLE
Operation
Read
WRITE BYTE a
WRITE BYTE b
WRITE BYTE c
WRITE BYTE d
WRITE ALL BYTEs
WRITE ABORT / NOP
WE\
H
L
L
L
L
L
L
Bwa\
X
L
H
H
H
L
H
BWb\
X
H
L
H
H
L
H
BWc\
X
H
H
L
H
L
H
BWd\
X
H
H
H
L
L
H
Notes:
1. X means “Don’t Care.”
2. All inputs in this table must beet setup and hold time around the rising edge of CLK.
INTERLEAVED BURST ADDRESS TABLE (MODE = V
DD
or NC)
External Address
A1 A0
00
01
10
11
1st Burst Address
A1 A0
01
00
11
10
2nd Burst Address
A1 A0
10
11
00
01
3rd Burst Address
A1 A0
11
10
01
00
AS5SS128K36
Rev. 2.8 09/11
Micross Components reserves the right to change products or specifications without notice.
5
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