74LCX125 — Low Voltage Quad Buffer with 5V Tolerant Inputs and Outputs
February 2008
74LCX125
Low Voltage Quad Buffer with 5V Tolerant
Inputs and Outputs
Features
■
5V tolerant inputs and outputs
■
2.3V–3.6V V
CC
specifications provided
■
6.0ns t
PD
max. (V
CC
=
3.3V), 10µA I
CC
max.
■
Power down high impedance inputs and outputs
■
Supports live insertion/withdrawal
(1)
■
±24mA output drive (V
CC
=
3.0V)
■
Implements
proprietary
noise/EMI reduction circuitry
■
Latch-up performance exceeds JEDEC 78 conditions
■
ESD performance:
General Description
The LCX125 contains four independent non-inverting
buffers with 3-STATE outputs. The inputs tolerate volt-
ages up to 7V allowing the interface of 5V systems to 3V
systems.
The 74LCX125 is fabricated with an advanced CMOS
technology to achieve high speed operation while main-
taining CMOS low power dissipation.
– Human body model
>
2000V
– Machine model
>
100V
■
Leadless DQFN package
Note:
1. To ensure the high-impedance state during power up
or down, OE should be tied to V
CC
through a pull-up
resistor: the minimum value of the resistor is
determined by the current-sourcing capability of the
driver.
Ordering Information
Order Number
74LCX125M
74LCX125SJ
74LCX125BQX
(2)
74LCX125MTC
Package
Number
M14A
M14D
MLP14A
MTC14
Package Description
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
14-Terminal Depopulated Quad Very-Thin Flat Pack No Leads (DQFN), JEDEC
MO-241, 2.5 x 3.0mm
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
Note:
2. DQFN package available in Tape and Reel only.
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
All packages are lead free per JEDEC: J-STD-020B standard.
©1995 Fairchild Semiconductor Corporation
74LCX125 Rev. 1.7.0
www.fairchildsemi.com
74LCX125 — Low Voltage Quad Buffer with 5V Tolerant Inputs and Outputs
Connection Diagrams
Pin Assignments for SOIC, SOP, and TSSOP
Logic Symbol
IEEE/IEC
(Top View)
Pad Assignments for DQFN
Truth Table
Inputs
OE
n
L
L
H
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
Z
=
High Impedance
X
=
Immaterial
Output
A
n
L
H
X
O
n
L
H
Z
(Top Through View)
Pin Description
Pin Names
A
n
OE
n
O
n
Description
Inputs
Output Enable Inputs
Outputs
©1995 Fairchild Semiconductor Corporation
74LCX125 Rev. 1.7.0
www.fairchildsemi.com
2
74LCX125 — Low Voltage Quad Buffer with 5V Tolerant Inputs and Outputs
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
V
CC
V
I
V
O
Supply Voltage
DC Input Voltage
DC Output Voltage,
Output in 3-STATE
Parameter
Rating
–0.5V to +7.0V
–0.5V to +7.0V
–0.5V to +7.0V
–0.5V to V
CC
+ 0.5V
–50mA
–50mA
+50mA
±50mA
±100mA
±100mA
–65°C to +150°C
Output in HIGH or LOW State
(3)
I
IK
I
OK
DC Input Diode Current, V
I
<
GND
DC Output Diode Current
V
O
<
GND
V
O
>
V
CC
I
O
I
CC
I
GND
T
STG
DC Output Source/Sink Current
DC Supply Current per Supply Pin
DC Ground Current per Ground Pin
Storage Temperature
Note:
3. I
O
Absolute Maximum Rating must be observed.
Recommended Operating Conditions
(4)
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to absolute maximum ratings.
Symbol
V
CC
Supply Voltage
Operating
Data Retention
V
I
V
O
Input Voltage
Output Voltage
HIGH or LOW State
3-STATE
I
OH
/ I
OL
Output Current
V
CC
=
3.0V–3.6V
V
CC
=
2.7V–3.0V
V
CC
=
2.3V–2.7V
T
A
∆
t /
∆
V
Parameter
Min.
2.0
1.5
0
0
0
Max.
3.6
3.6
5.5
V
CC
5.5
±24
±12
±8
Units
V
V
V
mA
Free-Air Operating Temperature
Input Edge Rate, V
IN
=
0.8V–2.0V, V
CC
=
3.0V
–40
0
85
10
°C
ns / V
Note:
4. Unused inputs must be held HIGH or LOW. They may not float.
©1995 Fairchild Semiconductor Corporation
74LCX125 Rev. 1.7.0
www.fairchildsemi.com
3
74LCX125 — Low Voltage Quad Buffer with 5V Tolerant Inputs and Outputs
DC Electrical Characteristics
T
A
=
–40°C to +85°C
Symbol
V
IH
V
IL
V
OH
Parameter
HIGH Level Input Voltage
LOW Level Input Voltage
HIGH Level Output Voltage
V
CC
(V)
2.3–2.7
2.7–3.6
2.3–2.7
2.7–3.6
2.3–3.6
2.3
2.7
3.0
Conditions
Min.
1.7
2.0
Max.
Units
V
0.7
0.8
I
OH
=
–100µA
I
OH
=
–8mA
I
OH
=
–12mA
I
OH
=
–18mA
I
OH
=
–24mA
I
OL
=
100µA
I
OL
=
8mA
I
OL
=
12mA
I
OL
=
16mA
I
OL
=
24mA
0
≤
V
I
≤
5.5V
0
≤
V
O
≤
5.5V,
V
I
=
V
IH
or V
IL
V
I
or V
O
=
5.5V
V
I
=
V
CC
or GND
3.6V
≤
V
I
, V
O
≤
5.5V
(5)
V
IH
=
V
CC
– 0.6V
V
CC
– 0.2
1.8
2.2
2.4
2.2
0.2
0.6
0.4
0.4
0.55
±5.0
±5.0
10
10
±10
500
V
V
V
OL
LOW Level Output Voltage
2.3–3.6
2.3
2.7
3.0
V
I
I
I
OZ
I
OFF
I
CC
∆I
CC
Input Leakage Current
3-STATE Output Leakage
Power-Off Leakage Current
Quiescent Supply Current
Increase in I
CC
per Input
2.3–3.6
2.3–3.6
0
2.3–3.6
2.3–3.6
µA
µA
µA
µA
µA
Note:
5. Outputs disabled or 3-STATE only.
AC Electrical Characteristics
T
A
=
–40°C to +85°C, R
L
=
500Ω
V
CC
=
3.3V ± 0.3V,
C
L
=
50 pF
Symbol
t
PHL
, t
PLH
t
PZL
, t
PZH
t
PLZ
, t
PHZ
V
CC
=
2.7V,
C
L
=
50 pF
Min.
1.5
1.5
1.5
V
CC
=
2.5V ± 0.2V,
C
L
=
30 pF
Min.
1.5
1.5
1.5
Parameter
Propagation Delay
Output Enable Time
Output Disable Time
Min.
1.5
1.5
1.5
Max.
6.0
7.0
6.0
1.0
Max.
6.5
8.0
7.0
Max.
7.2
9.1
7.2
Units
ns
ns
ns
ns
t
OSHL
, t
OSLH
Output to Output Skew
(6)
Note:
6. Skew is defined as the absolute value of the difference between the actual propagation delay for any two
separate outputs of the same device. The specification applies to any outputs switching in the same direction,
either HIGH-to-LOW (t
OSHL
) or LOW-to-HIGH (t
OSLH
).
©1995 Fairchild Semiconductor Corporation
74LCX125 Rev. 1.7.0
www.fairchildsemi.com
4
74LCX125 — Low Voltage Quad Buffer with 5V Tolerant Inputs and Outputs
Dynamic Switching Characteristics
T
A
=
25°C
Symbol
V
OLP
V
OLV
Parameter
Quiet Output Dynamic Peak V
OL
Quiet Output Dynamic Valley V
OL
V
CC
(V)
3.3
2.5
3.3
2.5
Conditions
C
L
=
50pF, V
IH
=
3.3V, V
IL
=
0V
C
L
=
30pF, V
IH
=
2.5V, V
IL
=
0V
C
L
=
50pF, V
IH
=
3.3V, V
IL
=
0V
C
L
=
30pF, V
IH
=
2.5V, V
IL
=
0V
Typical
0.8
0.6
–0.8
–0.6
Unit
V
V
Capacitance
Symbol
C
IN
C
OUT
C
PD
Parameter
Input Capacitance
Output Capacitance
Power Dissipation Capacitance
Conditions
V
CC
=
Open, V
I
=
0V or V
CC
V
CC
=
3.3V, V
I
=
0V or V
CC
V
CC
=
3.3V, V
I
=
0V or V
CC
, f
=
10MHz
Typical
7.0
8.0
25.0
Units
pF
pF
pF
©1995 Fairchild Semiconductor Corporation
74LCX125 Rev. 1.7.0
www.fairchildsemi.com
5
FPGA/CPLD
京公网安备 11010802033920号
EEWORLD
