ST16C554 datasheet, PDF - EEWORLD Datasheet

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ST16C554: DescriptionSerial I/O Controller,; CategoryThe embedded processor and controller Microcontrollers and processors; File Size721KB，39 Pages; ManufacturerMaxLinear Inc

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ST16C554 Overview

Serial I/O Controller,

ST16C554 Parametric

Parameter Name	Attribute value
Maker	MaxLinear Inc
Reach Compliance Code	unknown
uPs/uCs/peripheral integrated circuit type	SERIAL IO/COMMUNICATION CONTROLLER, SERIAL

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ST16C554 / ST16C554D / ST68C554

2.97V to 5.5V Quad UARTs with 16-Byte FIFO

Data Sheet

General Description

The ST16C554, ST16C554D and ST68C554 are each quad

Universal Asynchronous Receivers and Transmitters

(UARTs) with 16 bytes of transmit and receive FIFOs,

selectable receive FIFO trigger levels, and data rates of up to

1.5Mbps. Each UART has a set of registers that provide the

user with operating status and control, receiver error

indications, and modem serial interface controls. An internal

loopback capability allows onboard diagnostics. The

ST16C554 is available in a 64-pin LQFP package, the

ST16C554D is available in both a 64-pin LQFP and a 68-pin

PLCC package, and the ST68C554 is available in a 68-pin

PLCC package. The 64-pin package only offers the 16 mode

interface, but the 68-pin package offers an additional 68

mode interface which allows easy integration with Motorola

processors. The ST16C554CQ64 (64-pin) offers three-state

interrupt output while the ST16C554DCQ64 provides

continuous interrupt output. The ST16C554 and ST16C554D

combine the package interface modes of the 16C554 and

68C554 on a single integrated chip.

Features

■

Pin-to-pin compatible with the industry standard

ST16C454, ST68C454, ST68C554, TI’s TL16C554A and

Philips’ SC16C554B

Intel or Motorola data bus interface select

Four independent UART channels



Data rates of up to 1.5Mbps at 5V



Data rates of up to 500kbps at 3.3V



16 byte transmit FIFO



16 byte receive FIFO with error tags



4 selectable RX FIFO trigger levels



Full modem interface

2.97V to 5.5V supply operation

Crystal oscillator or external clock input

■

Applications

■

Portable appliances

Telecommunication network routers

Ethernet network routers

Cellular data devices

Factory automation and process controls

Ordering Information -

page 32

Block Diagram

A2:A0

D7:D0

IOR#

IOW#

CSA#

CSB#

CSC#

CSD#

INTA

INTB

INTC

INTD

TXRDY# A-D

RXRDY# A-D

Reset

16/ 68#

INTSEL

UART Channel D

(same as Channel A)

Crystal Osc / Buffer

UART Channel A

UART 16 Byte TX FIFO

Regs

TX & RX

ENDEC

BRG

16 Byte RX FIFO

UART Channel B

(same as Channel A)

UART Channel C

(same as Channel A)

2.97 V to 5.5 V VCC

GND

TXA, RXA, IRTXA, DTRA#,

DSRA#, RTSA#, CTSA#,

CDA#, RIA#

TXB, RXB, IRTXB, DTRB#,

DSRB#, RTSB#, CTSB#,

CDB#, RIB#

TXC, RXC, IRTXC, DTRC#,

DSRC#, RTSC#, CTSC#,

CDC#, RIC#

TXD, RXD, IRTXD, DTRD#,

DSRD#, RTSD#, CTSD#,

CDD#, RID#

XTAL1

XTAL2

Data Bus

Interface

Figure 1:

ST16C554 Block Diagram

• www.maxlinear.com•

Rev 4.0.2

ST16C554 / ST16C554D / ST68C554 2.97V to 5.5V Quad UARTs with 16-Byte FIFO Data Sheet

Table of Contents

General Description............................................................................................................................................. i

Features............................................................................................................................................................... i

Applications ......................................................................................................................................................... i

Block Diagram...................................................................................................................................................... i

1.0 Pin Information ............................................................................................................................................. 1

1.1 Pin Descriptions ......................................................................................................................................................2

2.0 Product Description ..................................................................................................................................... 5

2.1 Enhanced FIFO ...................................................................................................................................................... 5

2.2 Intel or Motorola Data Bus Interface....................................................................................................................... 5

2.3 Data Rate ............................................................................................................................................................... 5

2.4 Enhanced Features ................................................................................................................................................ 5

3.0 Functional Descriptions............................................................................................................................... 6

3.1 CPU Interface..........................................................................................................................................................6

3.2 Device Reset .......................................................................................................................................................... 7

3.3 Channel Selection .................................................................................................................................................. 7

3.4 Internal Registers of Channels A - D...................................................................................................................... 7

3.5 INT Outputs for Channels A - D ............................................................................................................................. 7

3.6 DMA Mode ..............................................................................................................................................................8

3.7 Crystal Oscillator or External Clock Input ................................................................................................................8

3.8 Programmable Baud Rate Generator..................................................................................................................... 9

3.9 Transmitter ............................................................................................................................................................10

3.9.1 Transmit Holding Register (THR) - Write Only ..........................................................................................10

3.9.2 Transmitter Operation in Non-FIFO Mode.................................................................................................10

3.9.3 Transmitter Operation in FIFO Mode ........................................................................................................10

3.10 Receiver ............................................................................................................................................................. 10

3.10.1 Receive Holding Register (RHR) - Read Only ........................................................................................11

3.11 Internal Loopback................................................................................................................................................12

4.0 UART Internal Registers ............................................................................................................................ 13

5.0 Internal Register Descriptions................................................................................................................... 15

5.1 Receive Holding Register (RHR) - Read-Only ..................................................................................................... 15

5.2 Transmit Holding Register (THR) - Write-Only ..................................................................................................... 15

5.3 Interrupt Enable Register (IER) - Read and Write ................................................................................................ 15

5.3.1 IER Versus Receive FIFO Interrupt Mode Operation................................................................................15

5.3.2 IER Versus Receive and Transmit FIFO Polled Mode Operation ............................................................. 15

9/4/19

Rev 4.0.2

iii

ST16C554 / ST16C554D / ST68C554 2.97V to 5.5V Quad UARTs with 16-Byte FIFO Data Sheet

Table of Contents

5.4 Interrupt Status Register (ISR) ............................................................................................................................. 16

5.4.1 Interrupt Generation ..................................................................................................................................16

5.4.2 Interrupt Clearing.......................................................................................................................................16

5.5 FIFO Control Register (FCR) - Write-Only ............................................................................................................ 17

5.6 Line Control Register (LCR) - Read and Write ..................................................................................................... 17

5.7 Modem Control Register (MCR) or General Purpose Output Control - Read and Write ...................................... 18

5.8 Line Status Register (LSR) - Read and Write....................................................................................................... 19

5.9 Modem Status Register (MSR) - Read and Write .................................................................................................20

5.10 Scratch Pad Register (SPR) - Read and Write................................................................................................... 20

5.11 Baud Rate Generator Registers (DLL and DLM) - Read and Write ................................................................... 21

6.0 Specifications ............................................................................................................................................. 22

6.1 Absolute Maximum Ratings...................................................................................................................................22

6.2 Electrical Characteristics .......................................................................................................................................22

6.2.1 DC Electrical Characteristics.....................................................................................................................22

6.2.2 AC Electrical Characteristics .....................................................................................................................23

7.0 Mechanical Dimensions ............................................................................................................................. 30

7.1 LQFP64 .................................................................................................................................................................30

7.2 PLCC68 .................................................................................................................................................................31

8.0 Ordering Information.................................................................................................................................. 32

9/4/19

Rev 4.0.2

ST16C554 / ST16C554D / ST68C554 2.97V to 5.5V Quad UARTs with 16-Byte FIFO Data Sheet

List of Figures

Figure 1: ST16C554 Block Diagram ...................................................................................................................... i

Figure 2: PLCC68 Pinout, Intel Mode ................................................................................................................... 1

Figure 3: PLCC68 Pinout, Motorola Mode............................................................................................................ 1

Figure 4: LQFP64 Pinout, Intel Mode Only........................................................................................................... 1

Figure 5: PLCC68 Pinout, Motorola Mode Only ................................................................................................... 1

Figure 6: ST16C554D Typical Intel and Motorola Data Bus Interconnections ..................................................... 6

Figure 7: Typical Crystal Connections .................................................................................................................. 8

Figure 8: Baud Rate Generator ............................................................................................................................ 9

Figure 9: Transmitter Operation in Non-FIFO Mode........................................................................................... 10

Figure 10: Transmitter Operation in FIFO Mode................................................................................................. 10

Figure 11: Receiver Operation in Non-FIFO Mode............................................................................................. 11

Figure 12: Receiver Operation in FIFO Mode..................................................................................................... 11

Figure 13: Internal Loopback in Channels A and B ............................................................................................ 12

Figure 14: Clock Timing...................................................................................................................................... 24

Figure 15: Modem Input and Output Timing for Channels A - D ........................................................................ 24

Figure 16: 16 Mode (Intel) Data Bus Read Timing for Channels A - D............................................................... 25

Figure 17: 16 Mode (Intel) Data Bus Write Timing for Channels A - D............................................................... 25

Figure 18: 68 Mode (Motorola) Data Bus Read Timing for Channels A - D ....................................................... 26

Figure 19: 68 Mode (Motorola) Data Bus Write Timing for Channels A - D........................................................ 26

Figure 20: Receive Ready and Interrupt Timing (Non-FIFO Mode) for Channels A - D ..................................... 27

Figure 21: Transmit Ready and Interrupt Timing (Non-FIFO Mode) for Channels A - D .................................... 27

Figure 22: Receive Ready and Interrupt Timing (FIFO Mode, DMA Disabled) for Channels A - D.................... 28

Figure 23: Receive Ready and Interrupt Timing (FIFO Mode, DMA Enabled) for Channels A - D..................... 28

Figure 24: Transmit Ready and Interrupt Timing (FIFO Mode, DMA Disabled) for Channels A - D................... 29

Figure 25: Transmit Ready and Interrupt Timing (FIFO Mode, DMA Enabled) for Channels A - D.................... 29

Figure 26: Mechanical Dimension, LQFP64 (10 x 10 x 1.4mm Low-Profile Quad Flat Pack) ............................ 30

Figure 27: Mechanical Dimensions, PLCC68 (Plastic Leaded Chip Carrier)...................................................... 31

9/4/19

Rev 4.0.2

ST16C554 Related Products

	ST16C554	ST68C554	ST16C554D
Description	Serial I/O Controller,	Serial I/O Controller,	Serial I/O Controller,
Reach Compliance Code	unknown	unknown	unknown
uPs/uCs/peripheral integrated circuit type	SERIAL IO/COMMUNICATION CONTROLLER, SERIAL	SERIAL IO/COMMUNICATION CONTROLLER, SERIAL	SERIAL IO/COMMUNICATION CONTROLLER, SERIAL
Maker	MaxLinear Inc	-	MaxLinear Inc

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