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DS90LT012ATLD

Description
LINE RECEIVER, DSO8, 3 X 3 MM, LLP-8
CategoryAnalog mixed-signal IC    Drivers and interfaces   
File Size929KB,9 Pages
ManufacturerRochester Electronics
Websitehttps://www.rocelec.com/
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DS90LT012ATLD Overview

LINE RECEIVER, DSO8, 3 X 3 MM, LLP-8

DS90LT012ATLD Parametric

Parameter NameAttribute value
Is it lead-free?Contains lead
Is it Rohs certified?incompatible
MakerRochester Electronics
Parts packaging codeSOIC
package instruction3 X 3 MM, LLP-8
Contacts8
Reach Compliance Codeunknown
Input propertiesDIFFERENTIAL
Interface integrated circuit typeLINE RECEIVER
Interface standardsEIA-644-A; TIA-644-A
JESD-30 codeS-XDSO-N8
JESD-609 codee0
length3 mm
Humidity sensitivity level1
Number of functions1
Number of terminals8
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Package body materialUNSPECIFIED
encapsulated codeHVSON
Package shapeSQUARE
Package formSMALL OUTLINE, HEAT SINK/SLUG, VERY THIN PROFILE
Peak Reflow Temperature (Celsius)235
Certification statusCOMMERCIAL
Maximum receive delay3.5 ns
Number of receiver bits1
Maximum seat height0.8 mm
Maximum supply voltage3.6 V
Minimum supply voltage2.7 V
Nominal supply voltage3.3 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal surfaceTIN LEAD
Terminal formNO LEAD
Terminal pitch0.5 mm
Terminal locationDUAL
Maximum time at peak reflow temperature30
width3 mm

DS90LT012ATLD Preview

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DS90LV012A/DS90LT012A 3V LVDS Single CMOS Differential Line Receiver
March 14, 2008
DS90LV012A/DS90LT012A
3V LVDS Single CMOS Differential Line Receiver
General Description
The DS90LV012A and DS90LT012A are single CMOS dif-
ferential line receivers designed for applications requiring
ultra low power dissipation, low noise, and high data rates.
The devices are designed to support data rates in excess of
400 Mbps (200 MHz) utilizing Low Voltage Differential Swing
(LVDS) technology
The DS90LV012A and DS90LT012A accept low voltage (350
mV typical) differential input signals and translates them to 3V
CMOS output levels. The receivers also support open, short-
ed, and terminated (100Ω) input fail-safe. The receiver output
will be HIGH for all fail-safe conditions. The DS90LV012A has
a pinout designed for easy PCB layout. The DS90LT012A in-
cludes an input line termination resistor for point-to-point
applications.
The DS90LV012A and DS90LT012A, and companion LVDS
line driver provide a new alternative to high power PECL/ECL
devices for high speed interface applications.
Features
Compatible with ANSI TIA/EIA-644-A Standard
>400 Mbps (200 MHz) switching rates
100 ps differential skew (typical)
3.5 ns maximum propagation delay
Integrated line termination resistor (102Ω typical)
Single 3.3V power supply design (2.7V to 3.6V range)
Power down high impedance on LVDS inputs
Accepts small swing (350 mV typical) differential signal
levels
LVDS receiver inputs accept LVDS/BLVDS/LVPECL
inputs
Supports open, short and terminated input fail-safe
Pinout simplifies PCB layout
Low Power Dissipation (10mW typical@ 3.3V static)
SOT-23 5-lead package
Leadless LLP-8 package (3x3 mm body size)
Electrically similar to the DS90LV018A
Fabricated with advanced CMOS process technology
Industrial temperature operating range
(−40°C to +85°C)
Connection Diagrams
Functional Diagram
DS90LV012A
20015002
20015026
DS90LT012A
(Top View)
Order Number DS90LV012ATMF, DS90LT012ATMF
See NS Package Number MF05A
20015025
Truth Table
INPUTS
[IN+] − [IN−]
V
ID
0V
20015027
OUTPUT
TTL OUT
H
L
H
(Top View)
Order Number DS90LV012ATLD, DS90LT012ATLD
See NS Package Number LDA08A
V
ID
−0.1V
Full Fail-safe OPEN/SHORT or
Terminated
© 2008 National Semiconductor Corporation
200150
www.national.com
DS90LV012A/DS90LT012A
Absolute Maximum Ratings
(Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (V
DD
)
−0.3V to +4V
Input Voltage (IN+, IN−)
−0.3V to +3.9V
Output Voltage (TTL OUT)
−0.3V to (V
DD
+ 0.3V)
Output Short Circuit Current
−100mA
Maximum Package Power Dissipation @ +25°C
LDA Package
2.26 W
Derate LDA Package
18.1 mW/°C above +25°C
Thermal resistance (θ
JA
)
MF Package
Derate MF Package
55.3°C/W
902mW
7.22 mW/°C above +25°C
Thermal resistance (θ
JA
)
Storage Temperature Range
Lead Temperature Range Soldering
(4 sec.)
Maximum Junction Temperature
ESD Ratings (Note 4)
138.5°C/W
−65°C to +150°C
+260°C
+150°C
Recommended Operating
Conditions
Supply Voltage (V
DD
)
Operating Free Air
Temperature (T
A
)
Min
+2.7
−40
Typ
+3.3
25
Max
+3.6
+85
Units
V
°C
Electrical Characteristics
Over Supply Voltage and Operating Temperature ranges, unless otherwise specified. (Notes 2, 3)
Symbol
V
TH
V
TL
V
CM
I
IN
Parameter
Differential Input High Threshold
Differential Input Low Threshold
Common-Mode Voltage
Input Current (DS90LV012A)
V
DD
= 2.7V, V
ID
= 100mV
V
DD
= 3.0V to 3.6V, V
ID
= 100mV
V
IN
= +2.8V
V
IN
= 0V
V
IN
= +3.6V
ΔI
IN
Change in Magnitude of I
IN
V
IN
= +2.8V
V
IN
= 0V
V
IN
= +3.6V
I
IND
R
T
C
IN
V
OH
Differential Input Current
(DS90LT012A)
Integrated Termination Resistor
(DS90LT012A)
Input Capacitance
Output High Voltage
IN+ = IN− = GND
I
OH
= −0.4 mA, V
ID
= +200 mV
I
OH
= −0.4 mA, Inputs terminated
I
OH
= −0.4 mA, Inputs shorted
V
OL
I
OS
V
CL
I
DD
Output Low Voltage
Output Short Circuit Current
Input Clamp Voltage
No Load Supply Current
I
OL
= 2 mA, V
ID
= −200 mV
V
OUT
= 0V (Note 5)
I
CL
= −18 mA
Inputs Open
V
DD
−15
−1.5
TTL OUT
2.4
2.4
2.4
V
DD
= 0V
3
V
IN+
= +0.4V, V
IN−
= +0V
V
IN+
= +2.4V, V
IN−
= +2.0V
V
DD
= 0V
V
DD
= 3.6V or 0V
V
DD
= 3.6V or 0V
Conditions
V
CM
dependant on V
DD
(Note 11)
Pin
IN+, IN−
−100
0.05
0.05
−10
−10
−20
4
4
4
3.9
102
3
3.1
3.1
3.1
0.3
−50
−0.7
5.4
9
0.5
−100
4.4
±1
±1
Min
Typ
−30
−30
2.35
V
DD
- 0.3V
+10
+10
+20
Max
0
Units
mV
mV
V
V
μA
μA
μA
μA
μA
μA
mA
pF
V
V
V
V
mA
V
mA
www.national.com
2
DS90LV012A/DS90LT012A
Switching Characteristics
Over Supply Voltage and Operating Temperature ranges, unless otherwise specified. (Notes 6, 7)
Symbol
t
PHLD
t
PLHD
t
SKD1
t
SKD3
t
SKD4
t
TLH
t
THL
f
MAX
Parameter
Differential Propagation Delay High to Low
Differential Propagation Delay Low to High
Differential Pulse Skew |t
PHLD
− t
PLHD
| (Note 8)
Differential Part to Part Skew (Note 9)
Differential Part to Part Skew (Note 10)
Rise Time
Fall Time
Maximum Operating Frequency (Note 12)
200
Conditions
C
L
= 15 pF
V
ID
= 200 mV
(Figure
1
and
Figure 2)
Min
1.0
1.0
0
0
0
Typ
1.8
1.7
100
0.3
0.4
350
175
250
Max
3.5
3.5
400
1.0
1.5
800
800
Units
ns
ns
ps
ns
ns
ps
ps
MHz
Note 1:
“Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices
should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation.
Note 2:
Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground unless otherwise
specified (such as V
ID
).
Note 3:
All typicals are given for: V
DD
= +3.3V and T
A
= +25°C.
Note 4:
ESD Ratings:
DS90LV012A:
HBM (1.5 kΩ, 100 pF)
2kV
EIAJ (0Ω, 200 pF)
900V
CDM
2000V
IEC direct (330Ω, 150 pF)
5kV
DS90LT012A:
HBM (1.5 kΩ, 100 pF)
2kV
EIAJ (0Ω, 200 pF)
700V
CDM
2000V
IEC direct (330Ω, 150 pF)
7kV
Note 5:
Output short circuit current (I
OS
) is specified as magnitude only, minus sign indicates direction only. Only one output should be shorted at a time, do not
exceed maximum junction temperature specification.
Note 6:
C
L
includes probe and jig capacitance.
Note 7:
Generator waveform for all tests unless otherwise specified: f = 1 MHz, Z
O
= 50Ω,
t
r
and t
f
(0% to 100%)
3 ns for IN±.
Note 8:
t
SKD1
is the magnitude difference in differential propagation delay time between the positive-going-edge and the negative-going-edge of the same channel.
Note 9:
t
SKD3
, part to part skew, is the differential channel-to-channel skew of any event between devices. This specification applies to devices at the same
V
DD
and within 5°C of each other within the operating temperature range.
Note 10:
t
SKD4
, part to part skew, is the differential channel-to-channel skew of any event between devices. This specification applies to devices over the
recommended operating temperature and voltage ranges, and across process distribution. t
SKD4
is defined as |Max − Min| differential propagation delay.
Note 11:
V
DD
is always higher than IN+ and IN− voltage. IN+ and IN− are allowed to have voltage range −0.05V to +2.35V when V
DD
= 2.7V and |V
ID
| / 2 to
V
DD
− 0.3V when V
DD
= 3.0V to 3.6V. V
ID
is not allowed to be greater than 100 mV when V
CM
= 0.05V to 2.35V when V
DD
= 2.7V or when V
CM
= |V
ID
| / 2 to
V
DD
− 0.3V when V
DD
= 3.0V to 3.6V.
Note 12:
f
MAX
generator input conditions: t
r
= t
f
< 1 ns (0% to 100%), 50% duty cycle, differential (1.05V to 1.35 peak to peak). Output criteria: 60%/40% duty
cycle, V
OL
(max 0.4V), V
OH
(min 2.4V), load = 15 pF (stray plus probes). The parameter is guaranteed by design. The limit is based on the statistical analysis of
the device over the PVT range by the transition times (t
TLH
and t
THL
).
Parameter Measurement Information
20015003
FIGURE 1. Receiver Propagation Delay and Transition Time Test Circuit
3
www.national.com
DS90LV012A/DS90LT012A
20015004
FIGURE 2. Receiver Propagation Delay and Transition Time Waveforms
Typical Applications
Balanced System
20015005
FIGURE 3. Point-to-Point Application (DS90LV012A)
Balanced System
20015028
FIGURE 4. Point-to-Point Application (DS90LT012A)
Applications Information
General application guidelines and hints for LVDS drivers and
receivers may be found in the following application notes:
LVDS Owner's Manual (lit #550062-002), AN-808, AN-977,
AN-971, AN-916, AN-805, AN-903.
LVDS drivers and receivers are intended to be primarily used
in an uncomplicated point-to-point configuration as is shown
in
Figure 3.
This configuration provides a clean signaling en-
vironment for the fast edge rates of the drivers. The receiver
is connected to the driver through a balanced media which
may be a standard twisted pair cable, a parallel pair cable, or
simply PCB traces. Typically the characteristic impedance of
the media is in the range of 100Ω. A termination resistor of
100Ω should be selected to match the media, and is located
as close to the receiver input pins as possible. The termination
resistor converts the driver output (current mode) into a volt-
age that is detected by the receiver. Other configurations are
possible such as a multi-receiver configuration, but the effects
of a mid-stream connector(s), cable stub(s), and other
impedance discontinuities as well as ground shifting, noise
margin limits, and total termination loading must be taken into
account.
www.national.com
4
The DS90LV012A and DS90LT012A differential line re-
ceivers are capable of detecting signals as low as 100 mV,
over a ±1V common-mode range centered around +1.2V.
This is related to the driver offset voltage which is typically
+1.2V. The driven signal is centered around this voltage and
may shift ±1V around this center point. The ±1V shifting may
be the result of a ground potential difference between the
driver's ground reference and the receiver's ground refer-
ence, the common-mode effects of coupled noise, or a com-
bination of the two. The AC parameters of both receiver input
pins are optimized for a recommended operating input volt-
age range of 0V to +2.4V (measured from each pin to ground).
The device will operate for receiver input voltages up to V
DD
,
but exceeding V
DD
will turn on the ESD protection circuitry
which will clamp the bus voltages.
POWER DECOUPLING RECOMMENDATIONS
Bypass capacitors must be used on power pins. Use high fre-
quency ceramic (surface mount is recommended) 0.1μF and
0.001μF capacitors in parallel at the power supply pin with the
smallest value capacitor closest to the device supply pin. Ad-
ditional scattered capacitors over the printed circuit board will
improve decoupling. Multiple vias should be used to connect

DS90LT012ATLD Related Products

DS90LT012ATLD DS90LT012ATMFX
Description LINE RECEIVER, DSO8, 3 X 3 MM, LLP-8 LINE RECEIVER, PDSO5, 1.60 MM, MO-178, SOT-23, 5 PIN
Is it lead-free? Contains lead Contains lead
Is it Rohs certified? incompatible incompatible
Maker Rochester Electronics Rochester Electronics
Parts packaging code SOIC SOIC
package instruction 3 X 3 MM, LLP-8 1.60 MM, MO-178, SOT-23, 5 PIN
Contacts 8 5
Reach Compliance Code unknown unknown
Input properties DIFFERENTIAL DIFFERENTIAL
Interface integrated circuit type LINE RECEIVER LINE RECEIVER
Interface standards EIA-644-A; TIA-644-A EIA-644-A; TIA-644-A
JESD-30 code S-XDSO-N8 R-PDSO-G5
JESD-609 code e0 e0
length 3 mm 2.92 mm
Humidity sensitivity level 1 1
Number of functions 1 1
Number of terminals 8 5
Maximum operating temperature 85 °C 85 °C
Minimum operating temperature -40 °C -40 °C
Package body material UNSPECIFIED PLASTIC/EPOXY
encapsulated code HVSON LSSOP
Package shape SQUARE RECTANGULAR
Package form SMALL OUTLINE, HEAT SINK/SLUG, VERY THIN PROFILE SMALL OUTLINE, LOW PROFILE, SHRINK PITCH
Peak Reflow Temperature (Celsius) 235 260
Certification status COMMERCIAL COMMERCIAL
Maximum receive delay 3.5 ns 3.5 ns
Number of receiver bits 1 1
Maximum seat height 0.8 mm 1.22 mm
Maximum supply voltage 3.6 V 3.6 V
Minimum supply voltage 2.7 V 2.7 V
Nominal supply voltage 3.3 V 3.3 V
surface mount YES YES
technology CMOS CMOS
Temperature level INDUSTRIAL INDUSTRIAL
Terminal surface TIN LEAD TIN LEAD
Terminal form NO LEAD GULL WING
Terminal pitch 0.5 mm 0.95 mm
Terminal location DUAL DUAL
Maximum time at peak reflow temperature 30 40
width 3 mm 1.6 mm

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