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74SSTUB32865AZJBR

Description
28-Bit to 56-Bit Registered Buffer with Address-Parity Test 160-NFBGA -40 to 85
Categorylogic    logic   
File Size768KB,21 Pages
ManufacturerTexas Instruments
Websitehttp://www.ti.com.cn/
Related ProductsFound20parts with similar functions to 74SSTUB32865AZJBR
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74SSTUB32865AZJBR Overview

28-Bit to 56-Bit Registered Buffer with Address-Parity Test 160-NFBGA -40 to 85

74SSTUB32865AZJBR Parametric

Parameter NameAttribute value
Brand NameTexas Instruments
Is it Rohs certified?incompatible
MakerTexas Instruments
Parts packaging codeBGA
package instructionTFBGA, BGA160,12X18,25
Contacts160
Reach Compliance Codecompli
ECCN codeEAR99
Factory Lead Time1 week
seriesSSTU
JESD-30 codeR-PBGA-B160
JESD-609 codee1
length13 mm
Logic integrated circuit typeD FLIP-FLOP
Maximum Frequency@Nom-Su410000000 Hz
MaximumI(ol)0.012 A
Humidity sensitivity level3
Number of digits28
Number of functions1
Number of terminals160
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Output characteristicsOPEN-DRAIN
Output polarityTRUE
Package body materialPLASTIC/EPOXY
encapsulated codeTFBGA
Encapsulate equivalent codeBGA160,12X18,25
Package shapeRECTANGULAR
Package formGRID ARRAY, THIN PROFILE, FINE PITCH
method of packingTR
Peak Reflow Temperature (Celsius)260
power supply1.8 V
Prop。Delay @ Nom-Su1.1 ns
propagation delay (tpd)3 ns
Certification statusNot Qualified
Maximum seat height1.2 mm
Maximum supply voltage (Vsup)1.9 V
Minimum supply voltage (Vsup)1.7 V
Nominal supply voltage (Vsup)1.8 V
surface mountYES
Temperature levelINDUSTRIAL
Terminal surfaceTin/Silver/Copper (Sn/Ag/Cu)
Terminal formBALL
Terminal pitch0.65 mm
Terminal locationBOTTOM
Maximum time at peak reflow temperatureNOT SPECIFIED
Trigger typePOSITIVE EDGE
width9 mm
minfmax410 MHz
Base Number Matches1

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