24LC21
1K 2.5V Dual Mode CMOS Serial EEPROM
FEATURES
• Single supply with operation down to 2.5V
• Completely implements DDC1
™
/DDC2
™
inter-
face for monitor identification
• Low power CMOS technology
- 1 mA active current typical
- 10
µ
A standby current typical at 5.5V
• Two wire serial interface bus, I
2
C
™
compatible
• Self-timed write cycle (including auto-erase)
• Page-write buffer for up to 8 bytes
• 100 kHz (2.5V) and 400 kHz (5V) compatibility
• Factory programming (QTP) available
• 1,000,000 erase/write cycles guaranteed*
• Data retention > 200 years
• 8 pin PDIP and SOIC package
• Available for extended temperature ranges
- Commercial:
0˚C to +70˚C
- Industrial:
-40˚C to +85˚C
PACKAGE TYPE
PDIP
NC
NC
NC
V
SS
1
2
3
4
8
V
CC
VCLK
SCL
SDA
24LC21
7
6
5
SOIC
NC
NC
NC
V
SS
1
2
8
7
V
CC
VCLK
SCL
SDA
24LC21
3
4
6
5
DESCRIPTION
The Microchip Technology Inc. 24LC21 is a 128 x 8 bit
Electrically Erasable PROM. This device is designed for
use in applications requiring storage and serial trans-
mission of configuration and control information. Two
modes of operation have been implemented: Transmit
Only Mode and Bi-Directional Mode. Upon power-up,
the device will be in the Transmit Only Mode, sending a
serial bit stream of the entire memory array contents,
clocked by the VCLK pin. A valid high to low transition
on the SCL pin will cause the device to enter the
Bi-Directional Mode, with byte selectable read/write
capability of the memory array. The 24LC21 is available
in a standard 8-pin PDIP and SOIC package in both
commercial and industrial temperature ranges.
BLOCK DIAGRAM
HV GENERATOR
I/O
CONTROL
LOGIC
MEMORY
CONTROL
LOGIC
XDEC
EEPROM
ARRAY
PAGE LATCHES
SDA
SCL
YDEC
VCLK
V
CC
V
SS
SENSE AMP
R/W CONTROL
*Future: 10,000,000 E/W cycles guaranteed
DDC is a trademark of the Video Electronics Standards Association.
I
2
C is a trademark of Philips Corporation.
©
1996 Microchip Technology Inc.
DS21095E-page 1
This document was created with FrameMaker 4 0 4
24LC21
1.0
1.1
ELECTRICAL CHARACTERISTICS
Maximum Ratings*
TABLE 1-1:
Name
V
SS
SDA
SCL
VCLK
V
CC
NC
PIN FUNCTION TABLE
Function
Ground
Serial Address/Data I/O
Serial Clock (Bi-Directional Mode)
Serial Clock (Transmit-Only Mode)
+2.5V to 5.5V Power Supply
No Connection
V
CC
........................................................................ 7.0V
All inputs and outputs w.r.t. V
SS
...... -0.6V to V
CC
+1.0V
Storage temperature ...........................-65˚C to +150˚C
Ambient temp. with power applied.......-65˚C to +125˚C
Soldering temperature of leads (10 seconds) ...+300˚C
ESD protection on all pins
......................................≥
4 kV
*
Notice:
Stresses above those listed under “Maximum ratings” may cause perma-
nent damage to the device. This is a stress rating only and functional operation of
the device at those or any other conditions above those indicated in the operational
listings of this specification is not implied. Exposure to maximum rating conditions
for extended periods may affect device reliability.
TABLE 1-2:
DC CHARACTERISTICS
V
CC
= +2.5V to 5.5V
Commercial (C): Tamb = 0˚C to +70˚C
Industrial
(I):
Tamb = -40˚C to +85˚C
Parameter
Symbol
V
IH
V
IL
V
IH
V
IL
V
HYS
V
OL1
V
OL2
I
LI
I
LO
C
IN
, C
OUT
I
CC
Write
I
CC
Read
I
CCS
Min
.7 V
CC
—
2.0
—
.05 V
CC
—
—
-10
-10
—
—
—
—
—
Max
—
.3 V
CC
.8
.2 V
CC
—
.4
.6
10
10
10
3
1
30
100
Units
V
V
V
V
V
V
V
µ
A
µ
A
pF
mA
mA
µ
A
µ
A
V
CC
≥
2.7V (Note 1)
V
CC
< 2.7V (Note 1)
Note 1
I
OL
= 3 mA, V
CC
= 2.5V (Note 1)
I
OL
= 6 mA, V
CC
= 2.5V
V
IN
= .1V to V
CC
V
OUT
= .1V to V
CC
V
CC
= 5.0V (Note1),
Tamb = 25
°
C, F
CLK
= 1 MHz
V
CC
= 5.5V, SCL = 400 kHz
V
CC
= 3.0V, SDA = SCL = V
CC
V
CC
= 5.5V, SDA = SCL = V
CC
Conditions
SCL and SDA pins:
High level input voltage
Low level input voltage
Input levels on VCLK pin:
High level input voltage
Low level input voltage
Hysteresis of Schmitt trigger inputs
Low level output voltage
Low level output voltage
Input leakage current
Output leakage current
Pin capacitance (all inputs/outputs)
Operating current
Standby current
Note 1: This parameter is periodically sampled and not 100% tested.
DS21095E-page 2
©
1996 Microchip Technology Inc.
24LC21
TABLE 1-3:
AC CHARACTERISTICS
Standard Mode
Parameter
Symbol
Min
Clock frequency
Clock high time
Clock low time
SDA and SCL rise time
SDA and SCL fall time
START condition hold time
START condition setup time
Data input hold time
Data input setup time
STOP condition setup time
Output valid from clock
Bus free time
F
CLK
T
HIGH
T
LOW
T
R
T
F
T
HD
:
STA
T
SU
:
STA
T
HD
:
DAT
T
SU
:
DAT
T
SU
:
STO
T
AA
T
BUF
—
4000
4700
—
—
4000
4700
0
250
4000
—
4700
Vcc= 4.5 - 5.5V
Fast Mode
Min
—
600
1300
—
—
600
600
0
100
600
—
1300
Units
Remarks
Max
100
—
—
1000
300
—
—
—
—
—
3500
—
Max
400
—
—
300
300
—
—
—
—
—
900
—
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note 1
Time the bus must be free
before a new transmission can
start
Note 2, C
B
≤
100 pF
Note 3
Byte or Page mode
Note 2
Note 2
After this period the first clock
pulse is generated
Only relevant for repeated
START condition
Note 1
Output fall time from V
IH
min
to V
IL
max
Input filter spike suppression
(SDA and SCL pins)
Write cycle time
T
OF
T
SP
T
WR
—
—
—
250
50
10
20 + .1
C
B
—
—
250
50
10
ns
ns
ms
Transmit-Only Mode Parameters
Output valid from VCLK
VCLK high time
VCLK low time
Mode transition time
Transmit-Only power up time
T
VAA
T
VHIGH
T
VLOW
T
VHZ
T
VPU
—
4000
4700
—
0
2000
—
—
500
—
—
600
1300
—
0
1000
—
—
500
—
ns
ns
ns
ns
ns
Note 1: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (min-
imum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
Note 2: Not 100% tested. C
B
= total capacitance of one bus line in pF.
Note 3: The combined T
SP
and V
HYS
specifications are due to new Schmitt trigger inputs which provide improved
noise and spike suppression. This eliminates the need for a T
I
specification for standard operation.
©
1996 Microchip Technology Inc.
DS21095E-page 3
24LC21
2.0
FUNCTIONAL DESCRIPTION
The 24LC21 operates in two modes, the Transmit-Only
Mode and the Bi-Directional Mode. There is a separate
two wire protocol to support each mode, each having a
separate clock input and sharing a common data line
(SDA). The device enters the Transmit-Only Mode upon
power-up. In this mode, the device transmits data bits
on the SDA pin in response to a clock signal on the
VCLK pin. The device will remain in this mode until a
valid high to low transition is placed on the SCL input.
When a valid transition on SCL is recognized, the
device will switch into the Bi-Directional Mode. The only
way to switch the device back to the Transmit-Only
Mode is to remove power from the device.
ninth, null bit (see Figure 2-1). The clock source for the
Transmit-Only Mode is provided on the VCLK pin, and
a data bit is output on the rising edge on this pin. The
eight bits in each byte are transmitted most significant
bit first. Each byte within the memory array will be out-
put in sequence. When the last byte in the memory
array is transmitted, the output will wrap around to the
first location and continue. The Bi-Directional Mode
Clock (SCL) pin must be held high for the device to
remain in the Transmit-Only Mode.
2.2
Initialization Procedure
2.1
Transmit-Only Mode
The device will power up in the Transmit-Only Mode.
This mode supports a unidirectional two wire protocol
for transmission of the contents of the memory array.
This device requires that it be initialized prior to valid
data being sent in the Transmit-Only Mode (see Initial-
ization Procedure, below). In this mode, data is trans-
mitted on the SDA pin in 8 bit bytes, each followed by a
After V
CC
has stabilized, the device will be in the Trans-
mit-Only Mode. Nine clock cycles on the VCLK pin
must be given to the device for it to perform internal
sychronization. During this period, the SDA pin will be
in a high impedance state. On the rising edge of the
tenth clock cycle, the device will output the first valid
data bit which will be the most significant bit of a byte.
The device will power up at an indeterminate byte
address. (See Figure 2-2).
FIGURE 2-1:
TRANSMIT ONLY MODE
SCL
T
VAA
SDA
Bit 1 (LSB)
VCLK
T
VHIGH
T
VLOW
T
VAA
Null Bit
Bit 8 (MSB)
Bit 7
FIGURE 2-2:
DEVICE INITIALIZATION
V
CC
SCL
High Impedance for 9 clock cycles
T
VPU
VCLK
1
2
8
9
10
11
T
VAA
Bit 8
T
VAA
Bit 7
SDA
DS21095E-page 4
©
1996 Microchip Technology Inc.
24LC21
3.0
BI-DIRECTIONAL MODE
3.1
The 24LC21 can be switched into the Bi-Directional
Mode (see Figure 3-1) by applying a valid high to low
transition on the Bi-Directional Mode Clock (SCL).
When the device has been switched into the Bi-Direc-
tional Mode, the VCLK input is disregarded, with the
exception that a logic high level is required to enable
write capability. This mode supports a two wire
bi-directional data transmission protocol. In this proto-
col, a device that sends data on the bus is defined to be
the transmitter, and a device that receives data from the
bus is defined to be the receiver. The bus must be con-
trolled by a master device that generates the Bi-Direc-
tional Mode Clock (SCL), controls access to the bus
and generates the START and STOP conditions, while
the 24LC21 acts as the slave. Both master and slave
can operate as transmitter or receiver, but the master
device determines which mode is activated.
Bi-Directional Mode Bus
Characteristics
The following
bus protocol
has been defined:
• Data transfer may be initiated only when the bus is
not busy.
• During data transfer, the data line must remain
stable whenever the clock line is HIGH. Changes
in the data line while the clock line is HIGH will be
interpreted as a START or STOP condition.
Accordingly, the following bus conditions have been
defined (see Figure 3-2).
3.1.1
BUS NOT BUSY (A)
Both data and clock lines remain HIGH.
3.1.2
START DATA TRANSFER (B)
A HIGH to LOW transition of the SDA line while the
clock (SCL) is HIGH determines a START condition. All
commands must be preceded by a START condition.
3.1.3
STOP DATA TRANSFER (C)
A LOW to HIGH transition of the SDA line while the
clock (SCL) is HIGH determines a STOP condition. All
operations must be ended with a STOP condition.
FIGURE 3-1:
MODE TRANSITION
Transmit Only Mode
SCL
T
VHZ
SDA
Bi-Directional Mode
VCLK
FIGURE 3-2:
(A)
SCL
(B)
DATA TRANSFER SEQUENCE ON THE SERIAL BUS
(D)
(D)
(C)
(A)
SDA
START CONDITION
ADDRESS
DATA ALLOWED
OR
TO CHANGE
ACKNOWLEDGE
VALID
STOP
CONDITION
©
1996 Microchip Technology Inc.
DS21095E-page 5
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