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NB2304AI1DTG

Description
2304 SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8, LEAD FREE, TSSOP-8
Categorylogic    logic   
File Size147KB,12 Pages
ManufacturerON Semiconductor
Websitehttp://www.onsemi.cn
Environmental Compliance  
Download Datasheet Parametric View All

NB2304AI1DTG Overview

2304 SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8, LEAD FREE, TSSOP-8

NB2304AI1DTG Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerON Semiconductor
Parts packaging codeSOIC
package instructionTSSOP,
Contacts8
Reach Compliance Codecompliant
series2304
Input adjustmentSTANDARD
JESD-30 codeS-PDSO-G8
JESD-609 codee3
length3 mm
Logic integrated circuit typePLL BASED CLOCK DRIVER
Number of functions1
Number of inverted outputs
Number of terminals8
Actual output times4
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Package body materialPLASTIC/EPOXY
encapsulated codeTSSOP
Package shapeSQUARE
Package formSMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Peak Reflow Temperature (Celsius)260
Certification statusNot Qualified
Same Edge Skew-Max(tskwd)0.2 ns
Maximum seat height1.1 mm
Maximum supply voltage (Vsup)3.6 V
Minimum supply voltage (Vsup)3 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal surfaceMATTE TIN
Terminal formGULL WING
Terminal pitch0.65 mm
Terminal locationDUAL
Maximum time at peak reflow temperature40
width3 mm
minfmax133.3 MHz
NB2304A
3.3V Zero Delay
Clock Buffer
The NB2304A is a versatile, 3.3 V zero delay buffer designed to
distribute high−speed clocks in PC, workstation, datacom, telecom
and other high−performance applications. It is available in an 8 pin
package. The part has an on−chip PLL which locks to an input clock
presented on the REF pin. The PLL feedback is required to be driven
to FBK pin, and can be obtained from one of the outputs. The
input−to−output propagation delay is guaranteed to be less than
250 ps, and the output−to−output skew is guaranteed to be less than
200 ps.
The NB2304A has two Banks of two outputs each. Multiple
NB2304A devices can accept the same input clock and distribute it. In
this case, the skew between the outputs of the two devices is
guaranteed to be less than 500 ps.
The NB2304A is available in two different configurations (Refer to
NB2304A Configurations Table). The NB2304Ax1* is the base part,
where the output frequencies equal the reference if there is no counter
in the feedback path. The NB2304Ax1H is the high−drive version of
the
−1
and the rise and fall times on this device are much faster.
The NB2304Ax2 allows the user to obtain REF, 1/2 X and 2X
frequencies on each output Bank. The exact configuration and output
frequencies depend on which output drives the feedback pin.
The NB2304Ax5H is a high−drive version with REF/2 on both
Banks.
Features
http://onsemi.com
MARKING
DIAGRAMS*
8
8
1
SOIC−8
D SUFFIX
CASE 751
1
8
8
1
TSSOP−8
DT SUFFIX
CASE 948R
1
XXXX
ALYW
XXXX
ALYW
XXXX
A
L
Y
W
= Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
Zero Input
Output Propagation Delay, Adjustable by Capacitive
Load on FBK Input
Multiple Configurations
Refer to NB2304A Configurations Table
Input Frequency Range: 10 MHz to 133 MHz
Multiple Low−Skew Outputs
Output−Output Skew < 200 ps
Device−Device Skew < 500 ps
Two Banks of Four Outputs
Less than 200 ps Cycle−to−Cycle Jitter (−1,
−1H, −5H)
Available in Space Saving, 8 pin 150 mil SOIC Packages and
Standard TSSOP
3.3 V Operation
Advanced 0.35
m
CMOS Technology
Industrial Temperature Available
Pb−Free Packages are Available
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 9 of this data sheet.
*x = C for Commercial; I for Industrial.
©
Semiconductor Components Industries, LLC, 2005
February, 2005
Rev. 0
1
Publication Order Number:
NB2304A/D
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