FUJITSU SEMICONDUCTOR
DATA SHEET
DS05-11052-1E
MEMORY
CMOS
4
×
512 K
×
32 BIT
SYNCHRONOUS DYNAMIC RAM
MB811L643242B
-10/-12/-15/-10L/-12L/-15L
CMOS 4-Bank
×
524,288-Word
×
32 Bit
Synchronous Dynamic Random Access Memory
s
DESCRIPTION
The Fujitsu MB811L643242B is a CMOS Synchronous Dynamic Random Access Memory (SDRAM) containing
67,108,864 memory cells accessible in a 32-bit format. The MB811L643242B features a fully synchronous
operation referenced to a positive edge clock whereby all operations are synchronized at a clock input which
enables high performance and simple user interface coexistence. The MB811L643242B SDRAM is designed to
reduce the complexity of using a standard dynamic RAM (DRAM) which requires many control signal timing
constraints, and may improve data bandwidth of memory as much as 5 times more than a standard DRAM.
The MB811L643242B is ideally suited for workstations, personal computers, laser printers, high resolution graphic
adapters/accelerators and other applications where an extremely large memory and bandwidth are required and
where a simple interface is needed.
s
PRODUCT LINE & FEATURES
Parameter
CL - t
RCD
- t
RP
Clock Frequency
Burst Mode Cycle Time
Access Time from Clock
CL = 2
CL = 3
CL = 2
CL = 3
CL = 2
CL = 3
MB811L643242B
-10/-10L
-12/-12L
-15/-15L
2 - 2 - 2 clk min.
2 - 2 - 2 clk min.
2 - 2 - 2 clk min.
3 - 3 - 3 clk min.
3 - 3 - 3 clk min.
3 - 3 - 3 clk min.
100 MHz max.
84 MHz max.
67 MHz max.
15 ns min.
17 ns min.
20ns min.
10 ns min.
12 ns min.
15 ns min.
8 ns max.
8 ns max.
8 ns max.
8 ns max.
8 ns max.
8 ns max.
130 mA max.
120 mA max.
110 mA max.
2 mA max.(std version) / 1.5 mA max.(L version)
2 mA max.(std. version) / 0.5 mA max.(L version)
Operating Current
Power Down Mode Current (I
CC2P
)
Self Refresh Current (I
CC6
)
•
•
•
•
•
Single +2.5 V Supply ±0.2 V tolerance
LVTTL compatible I/O interface
4 K refresh cycles every 64 ms
Four bank operation
Burst read/write operation and burst
read/single write operation capability
• Programmable burst type, burst length, and
CAS latency
• Auto-and Self-refresh (every 15.6
µs)
• CKE power down mode
• Output Enable and Input Data Mask
MB811L643242B
-10/-12/-15/-10L/-12L/-15L
s
PACKAGE
86-pin plastic TSOP(II)
(FPT-86P-M01)
Package and Ordering Information
– 86-pin plastic (400 mil) TSOP-II, order as MB811L643242B-×××FN (standard-version) or
MB811L643242B-×××LFN (L-version)
2
MB811L643242B
-10/-12/-15/-10L/-12L/-15L
s
PIN ASSIGNMENTS AND DESCRIPTIONS
86-Pin TSOP(II)
(TOP VIEW)
<Normal Bend: FPT-86P-M01>
V
DD
DQ
0
V
DDQ
DQ
1
DQ
2
V
SSQ
DQ
3
DQ
4
V
DDQ
DQ
5
DQ
6
V
SSQ
DQ
7
N.C.
V
DD
DQM
0
WE
CAS
RAS
CS
N.C.
A
12
A
11
A
10
/AP
A
0
A
1
A
2
DQM
2
V
DD
N.C.
DQ
16
V
SSQ
DQ
17
DQ
18
V
DDQ
DQ
19
DQ
20
V
SSQ
DQ
21
DQ
22
V
DDQ
DQ
23
V
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
V
SS
DQ
15
V
SSQ
DQ
14
DQ
13
V
DDQ
DQ
12
DQ
11
V
SSQ
DQ
10
DQ
9
V
DDQ
DQ
8
N.C.
V
SS
DQM
1
N.C.
N.C.
CLK
CKE
A
9
A
8
A
7
A
6
A
5
A
4
A
3
DQM
3
V
SS
N.C.
DQ
31
V
DDQ
DQ
30
DQ
29
V
SSQ
DQ
28
DQ
27
V
DDQ
DQ
26
DQ
25
V
SSQ
DQ
24
V
SS
Pin Number
1, 3, 9, 15, 29, 35, 41, 43, 49, 55, 75, 81
2, 4, 5, 7, 8, 10, 11, 13, 31, 33, 34, 36,
37, 39, 40, 42, 45, 47, 48, 50, 51, 53,
54, 56, 74, 76, 77, 79, 80, 82, 83, 85
6, 12, 32, 38, 44, 46, 52, 58, 72, 78, 84,
86
14, 21, 30, 57, 69, 70, 73
17
18
19
20
22, 23
24
24, 25, 26, 27, 60, 61, 62, 63, 64, 65, 66
67
68
16, 28, 59, 71
Symbol
V
DD
, V
DDQ
DQ
0
to DQ
31
V
SS
, V
SSQ
N.C.
WE
CAS
RAS
CS
A
11
(BA
1
), A
12
(BA
0
)
AP
A
0
to A
10
CKE
CLK
DQM
0
to DQM
3
Supply Voltage
Data I/O
Ground
No Connection
Write Enable
Function
Column Address Strobe
Row Address Strobe
Chip Select
Bank Select (Bank Address)
Auto Precharge Enable
Address Input
Clock Enable
Clock Input
Input Mask/Output Enable
3
• Row: A
0
to A
10
• Column: A
0
to A
7
MB811L643242B
-10/-12/-15/-10L/-12L/-15L
s
BLOCK DIAGRAM
Fig. 1 – MB811L643242B BLOCK DIAGRAM
CLK
To each block
CLOCK
BUFFER
CKE
BANK-3
BANK-2
BANK-1
BANK-0
RAS
CS
CONTROL
SIGNAL
LATCH
COMMAND
DECODER
CAS
RAS
CAS
WE
WE
MODE
REGISTER
A
0
to A
10
,
A
10
/AP
DRAM
CORE
(2,048
×
256
×
32)
ADDRESS
BUFFER/
REGISTER
A
11
(BA
1
)
A
12
(BA
0
)
ROW
ADDR.
DQM
0
to
DQM
3
COLUMN
ADDRESS
COUNTER
I/O DATA
BUFFER/
REGISTER
COL.
ADDR.
I/O
V
DD
V
DDQ
V
SS
/V
SSQ
DQ
0
to
DQ
31
4
MB811L643242B
-10/-12/-15/-10L/-12L/-15L
s
FUNCTIONAL TRUTH TABLE Note 1
COMMAND TRUTH TABLE
Function
Device Deselect
No Operation
Burst Stop
Read
Read with Auto-precharge
Write
Write with Auto-precharge
Bank Active
Precharge Single Bank
Precharge All Banks
Mode Register Set
Notes:
*1.
*2.
*3.
*4.
*5.
*6.
*8, 9
Note 2, 3, and 4
Notes
Symbol
*5
*5
DESL
NOP
BST
*6 READ
*6 READA
*6
WRIT
CKE
n-1
H
H
H
H
H
H
H
H
H
H
H
n
X
X
X
X
X
X
X
X
X
X
X
CS RAS CAS WE
H
L
L
L
L
L
L
L
L
L
L
X
H
H
H
H
H
H
L
L
L
L
X
H
H
L
L
L
L
H
H
H
L
X
H
L
H
H
L
L
H
L
L
L
A
12
, A
10
A
9
A
11
to
(BA) (AP) A
8
X
X
X
V
V
V
V
V
V
X
L
X
X
X
L
H
L
H
V
L
H
L
X
X
X
X
X
X
X
V
X
X
V
A
7
to
A
0
X
X
X
V
V
V
V
V
X
X
V
*6 WRITA
*7
ACTV
PRE
PALL
MRS
V = Valid, L = Logic Low, H = Logic High, X = either L or H.
All commands assumes no CSUS command on previous rising edge of clock.
All commands are assumed to be valid state transitions.
All inputs are latched on the rising edge of clock.
NOP and DESL commands have the same effect on the part.
READ, READA, WRIT and WRITA commands should only be issued after the corresponding bank has
been activated (ACTV command). Refer to STATE DIAGRAM.
*7. ACTV command should only be issued after corresponding bank has been precharged (PRE or PALL
command).
*8. Required after power up.
*9. MRS command should only be issued after all banks have been precharged (PRE or PALL command).
Refer to STATE DIAGRAM.
5